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Mon, 13 Feb 2017 08:26:15 +0000 (GMT) X-AuditID: b6c32a59-f79be6d0000012bb-4c-58a16da8a6a5 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id 4B.E2.06428.7AD61A85; Mon, 13 Feb 2017 17:26:15 +0900 (KST) Received: from localhost.localdomain ([10.113.62.216]) by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OLB000LO0RQDO60@mmp1.samsung.com>; Mon, 13 Feb 2017 17:26:15 +0900 (KST) From: Jaehoon Chung To: linux-pci@vger.kernel.org Cc: bhelgaas@google.com, krzk@kernel.org, linux-kernel@vger.kernel.org, jingoohan1@gmail.com, javier@osg.samsung.com, kgene@kernel.org, linux-samsung-soc@vger.kernel.org, cpgs@samsung.com, niyas.ahmed@samsung.com, alim.akhtar@samsung.com, pankaj.dubey@samsung.com, kishon@ti.com, devicetree@vger.kernel.org, mark.rutland@arm.com, vivek.gautam@codeaurora.org, robh+dt@kernel.org, Jaehoon Chung Subject: [PATCH V3 3/4] Documetation: binding: modify the exynos5440 pcie binding Date: Mon, 13 Feb 2017 17:26:12 +0900 Message-id: <20170213082613.19628-4-jh80.chung@samsung.com> X-Mailer: git-send-email 2.10.2 In-reply-to: <20170213082613.19628-1-jh80.chung@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAAzVSWUwTURT1zbQzrbE6VsUX3HCCC0QqUyg8FNxjJtEYAh8ixuAIE4q209pp jfph1ESQYot1i6AiKFBEiNpQcF9qFWPEqmhQDGBUPnANikbcxw7m/Zzz3j3nvHtzVbi2hIhU FQh23iZwJpoYrmi+GRMbV2euyor3HBmFXlQ0E6h6pxH1BWLQ8eB9JXr3vgFDT78XKlHdQBmJ Sl+9xdGD3j0ECoXOkqj94lECtVW0Euhw6CqGajoeYuj1gZdKdMI/QKJdV4IkujN4Hl+gZRsq GgDb7nZh7IXyLpKt9DlYX30xwTaVSszdVA/Y1qctGPvZNzldnc2nGnkuj7dF8UKuJa9AyE+j l2XmLM4xJMUzcUwKSqajBM7Mp9FLlqfHLS0wSe3QUZs4k0O6SudEkZ49L9Vmcdj5KKNFtKfR qxlGr2Pik3V6vV6XmLBmjt4glazljd7eQYX1UMTm621vFduBV+sEahWkEmFtxzVMxhHwQfcZ wgmGq7RUDYCnS12kTIow6O5rJv4rGs+0KOUHL4DV5R5MJt8AdF79Q/6rIqhZsOVra9h3LDUJ 9rdfDvviVCMO+/t9YasxVCa8+PEO+IcV1DT4pbYoLNZQc+FvV+VQ3BRYFQqGjdRUKvQdvxFO g1Q3CQMHndI/VBKZBH3Xcbl+CdzfeBvIeAx809pEyngC/FXTCWRtCYC/B84RMtkDYKf/9NAI EmDPi+6wE06NhK4frzE5QAN3Fw5NjIXeXQ0KGS+Ez84+UsjtlwJYfOkusRdMrATD6kEEbxXN +bxosBp0ImcWHUK+Ltdi9oHwIsauOg8el2UEAKUC9AgN6qrM0iq5TeIWcwBAFU6P1fwsqMrS avK4LVt5myXH5jDxYgAYpEF58MhxuRZprQV7DpOYxCTqU6STzCTT4zXZ8Z4sLZXP2fkNPG/l bf91mEoduR0snlDmLjywecdjD3Ork/n1ZKslukRzeKXx0UnDh/E183sC022nrhwb1d+7Pugv WjRrZtex5jjB3LSmvXZdl7UvJaba7x3cGIy+61BsKz5XvvGy77kgiJmupNErHB93T/kUva9N vTz0ahCYsB4n7HAv/JntTV+0d3LG1Bn3dGzCTD+tEI0cE4vbRO4vMVM2kZ4DAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrGIsWRmVeSWpSXmKPExsVy+t9jAd3luQsjDG6s17F4MG8bm8WSpgyL l4c0LeYfOcdq8ebtGiaLG7/aWC1WfJnJbtH/+DWzxYWnPWwW589vYLe4vGsOm8XZecfZLGac 38dksfT6RSaLJ1MesVos2vqF3aJ17xF2ixM/dzA7CHmsmbeG0eNyXy+Tx85Zd9k9Fmwq9di0 qpPNY0s/kNe3ZRWjx/Eb25k8Pm+SC+CMcrPJSE1MSS1SSM1Lzk/JzEu3VQoNcdO1UFLIS8xN tVWK0PUNCVJSKEvMKQXyjAzQgINzgHuwkr5dglvG8qc/WQqmiVUcOPuapYFxuVAXIyeHhICJ xNr121khbDGJC/fWs3UxcnEICSxllLi+9SsLhPODUeLlvZdgVWwCOhLbvx1nArFFBGQlPl7e A9bBLLCaWWLvlMPMIAlhgWCJXe9PMILYLAKqEl+XtbOD2LwC1hL/ehewQayTl1h4/gjYIE4B G4lN8w+C2UJANUdXzWaewMi7gJFhFaNEakFyQXFSeq5RXmq5XnFibnFpXrpecn7uJkZwnD2T 3sF4eJf7IUYBDkYlHt4f7xdECLEmlhVX5h5ilOBgVhLh/ZO5MEKINyWxsiq1KD++qDQntfgQ oynQYROZpUST84EpIK8k3tDE3MTc2MDC3NLSxEhJnLdx9rNwIYH0xJLU7NTUgtQimD4mDk6p BsYJ+csMiueuepc5M7f8zMINqtu8G1RP7ufY7/1F/JevlOhRy7e8s6dpJxiaHNzR026QZrc0 Zr6esKp+9U6OStbn/w5vf9Fvuv7o3cKt7PMf3Vm2Muq9qtsHp7IFm3t5bIP+uu78XitX8PDV l+v+4adWWu2OiKn3Xb1+jeyi96uLWx8tO7tM98JlJZbijERDLeai4kQA5mp7G8kCAAA= X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170213082615epcas5p24028ab4bd4fabbbcdf37ff36f0ee27a2 X-Msg-Generator: CA X-Sender-IP: 203.254.230.27 X-Local-Sender: =?UTF-8?B?7KCV7J6s7ZuIG1RpemVuIFBsYXRmb3JtIExhYihTL1fshLw=?= =?UTF-8?B?7YSwKRvsgrzshLHsoITsnpAbUzUo7LGF7J6EKS/ssYXsnoQ=?= X-Global-Sender: =?UTF-8?B?SmFlaG9vbiBDaHVuZxtUaXplbiBQbGF0Zm9ybSBMYWIuG1Nh?= =?UTF-8?B?bXN1bmcgRWxlY3Ryb25pY3MbUzUvU2VuaW9yIEVuZ2luZWVy?= X-Sender-Code: =?UTF-8?B?QzEwG1NUQUYbQzEwVjgxMTE=?= CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-HopCount: 7 X-CMS-RootMailID: 20170213082615epcas5p24028ab4bd4fabbbcdf37ff36f0ee27a2 X-RootMTR: 20170213082615epcas5p24028ab4bd4fabbbcdf37ff36f0ee27a2 References: <20170213082613.19628-1-jh80.chung@samsung.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP According to using PHY framework, updates the exynos5440-pcie binding. For maintaining backward compatibility, leaves the current dt-binding. (It should be deprecated.) Recommends to use the Phy Framework and "config" property to follow the designware-pcie binding. If you use the old way, can see "mssing *config* reg space" message. Because the getting configuration space address from range is old way. NOTE: When use the "config" property, first name of 'reg-names' must be set to "elbi". Otherwise driver can't maintain the backward capability. Signed-off-by: Jaehoon Chung Acked-by: Rob Herring Reviewed-by: Pankaj Dubey Reviewed-by: Alim Akhtar --- Changelog on V3: - Fixes a typo Changelog on V2: - Describes more commit message - Fixes the typos - Adds the new example for using PHY framework - Deprecated the old dt-binding description - Removes 'phy-names' .../bindings/pci/samsung,exynos5440-pcie.txt | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt index 4f9d23d..7d3b094 100644 --- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt +++ b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt @@ -7,8 +7,19 @@ Required properties: - compatible: "samsung,exynos5440-pcie" - reg: base addresses and lengths of the pcie controller, the phy controller, additional register for the phy controller. + (Registers for the phy controller are DEPRECATED. + Use the PHY framework.) +- reg-names : First name should be set to "elbi". + And use the "config" instead of getting the confgiruation address space + from "ranges". + NOTE: When use the "config" property, reg-names must be set. - interrupts: A list of interrupt outputs for level interrupt, pulse interrupt, special interrupt. +- phys: From PHY binding. Phandle for the Generic PHY. + Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt + +Other common properties refer to + Documentation/devicetree/binding/pci/designware-pcie.txt Example: @@ -54,6 +65,24 @@ SoC specific DT Entry: num-lanes = <4>; }; +With using PHY framework: + pcie_phy0: pcie-phy@270000 { + ... + reg = <0x270000 0x1000>, <0x271000 0x40>; + reg-names = "phy", "block"; + ... + }; + + pcie@290000 { + ... + reg = <0x290000 0x1000>, <0x40000000 0x1000>; + reg-names = "elbi", "config"; + phys = <&pcie_phy0>; + ranges = <0x81000000 0 0 0x60001000 0 0x00010000 + 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; + ... + }; + Board specific DT Entry: pcie@290000 {