From patchwork Mon Mar 27 09:45:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 9646041 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EC61D60328 for ; Mon, 27 Mar 2017 09:53:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C285128358 for ; Mon, 27 Mar 2017 09:53:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B73532833B; Mon, 27 Mar 2017 09:53:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4B8C928249 for ; Mon, 27 Mar 2017 09:53:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752748AbdC0Jts (ORCPT ); Mon, 27 Mar 2017 05:49:48 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:63013 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752759AbdC0JsQ (ORCPT ); Mon, 27 Mar 2017 05:48:16 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v2R9kW73001344; Mon, 27 Mar 2017 04:46:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1490607992; bh=0ykrAr3e1dDe77JyXxAgKSsfBCvuhwh4cEh2wdwTPYE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=HS8ByIkf7BDceecqFmOSdra6tRf+eUmzMaTD0SPbotmYB1hDzu3NzOXISRUfMvUKo iOu/BAzs7ArCPm28inbifv+5SmVnJJb1Ewcty48+BRvQpQjUNQaaTGEoNOtDiA+68p y/C1UU8C+2CeVIBYxcscGEmjWbH0Q3Hp9O85+Ny0= Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2R9kR2H021439; Mon, 27 Mar 2017 04:46:27 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Mon, 27 Mar 2017 04:46:26 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2R9jQIk012055; Mon, 27 Mar 2017 04:46:24 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Joao Pinto , , , , , , CC: , , Subject: [PATCH v5 16/24] dt-bindings: PCI: dra7xx: Add dt bindings to enable unaligned access Date: Mon, 27 Mar 2017 15:15:12 +0530 Message-ID: <20170327094520.3129-17-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170327094520.3129-1-kishon@ti.com> References: <20170327094520.3129-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Update device tree binding documentation of TI's dra7xx PCI controller to include property for enabling unaligned mem access. Signed-off-by: Kishon Vijay Abraham I Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/ti-pci.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt index 190828a5f32a..b69dd7dbd29e 100644 --- a/Documentation/devicetree/bindings/pci/ti-pci.txt +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -39,6 +39,11 @@ DEVICE MODE - interrupts : one interrupt entries must be specified for main interrupt. - num-ib-windows : number of inbound address translation windows - num-ob-windows : number of outbound address translation windows + - ti,syscon-unaligned-access: phandle to the syscon dt node. The 1st argument + should contain the register offset within syscon + and the 2nd argument should contain the bit field + for setting the bit to enable unaligned + access. Optional Property: - gpios : Should be added if a gpio line is required to drive PERST# line