From patchwork Mon Mar 27 09:49:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Pieralisi X-Patchwork-Id: 9646175 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0FC2A602BF for ; Mon, 27 Mar 2017 10:01:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DEBBA27F80 for ; Mon, 27 Mar 2017 10:01:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D37322836D; Mon, 27 Mar 2017 10:01:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 33B3627F80 for ; Mon, 27 Mar 2017 10:01:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752425AbdC0KBk (ORCPT ); Mon, 27 Mar 2017 06:01:40 -0400 Received: from foss.arm.com ([217.140.101.70]:60174 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752369AbdC0KBh (ORCPT ); Mon, 27 Mar 2017 06:01:37 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BAFDD1478; Mon, 27 Mar 2017 02:50:16 -0700 (PDT) Received: from red-moon.cambridge.arm.com (red-moon.cambridge.arm.com [10.1.206.55]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9CB7E3F23B; Mon, 27 Mar 2017 02:50:11 -0700 (PDT) From: Lorenzo Pieralisi To: linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Lorenzo Pieralisi , Arnd Bergmann , Russell King , Will Deacon , Catalin Marinas , Pratyush Anand , Jingoo Han , Bjorn Helgaas , Mingkai Hu , John Garry , Tanmay Inamdar , Murali Karicheri , Bharat Kumar Gogada , Ray Jui , Wenrui Li , Shawn Lin , Minghuan Lian , Jon Mason , Gabriele Paoloni , Thomas Petazzoni , Joao Pinto , Thierry Reding , Michal Simek , Stanimir Varbanov , Zhou Wang , Roy Zang , "Luis R. Rodriguez" Subject: [PATCH v2 06/22] ARM: implement ioremap_nopost() interface Date: Mon, 27 Mar 2017 10:49:34 +0100 Message-Id: <20170327094954.7162-7-lorenzo.pieralisi@arm.com> X-Mailer: git-send-email 2.10.0 In-Reply-To: <20170327094954.7162-1-lorenzo.pieralisi@arm.com> References: <20170327094954.7162-1-lorenzo.pieralisi@arm.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The PCI bus specifications (rev 3.0, 3.2.5 "Transaction Ordering and Posting") define rules for PCI configuration space transactions ordering and posting, that state that configuration writes have to be non-posted transactions. Current ioremap interface on ARM provides mapping functions that provide "bufferable" writes transactions (ie ioremap uses MT_DEVICE memory type) aka posted writes, so PCI host controller drivers have no arch interface to remap PCI configuration space with memory attributes that comply with the PCI specifications for configuration space. Implement an ARM specific ioremap_nopost() interface that allows to map PCI config memory regions with MT_UNCACHED memory type (ie strongly ordered - non-posted writes), providing a remap function that complies with PCI specifications for config space transactions. Signed-off-by: Lorenzo Pieralisi Cc: Arnd Bergmann Cc: Russell King --- arch/arm/include/asm/io.h | 10 ++++++++++ arch/arm/mm/ioremap.c | 7 +++++++ arch/arm/mm/nommu.c | 9 +++++++++ 3 files changed, 26 insertions(+) diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 42871fb..49913d1 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -352,6 +352,7 @@ static inline void memcpy_toio(volatile void __iomem *to, const void *from, * mapping has specific properties. * * Function Memory type Cacheability Cache hint + * ioremap_nopost() SO n/a n/a * ioremap() Device n/a n/a * ioremap_nocache() Device n/a n/a * ioremap_cache() Normal Writeback Read allocate @@ -372,6 +373,12 @@ static inline void memcpy_toio(volatile void __iomem *to, const void *from, * compiler may generate unaligned accesses - eg, via inlining its own * memcpy. * + * ioremap_nopost() maps memory as strongly ordered, to be used for + * specific mappings (eg PCI config space) that require non-posted + * write transactions. Strongly ordered transactions are ordered wrt + * device mappings, which means that ioremap_nopost() is the same + * as ioremap() except for non-posted writes behaviour. + * * All normal memory mappings have the following properties: * - reads can be repeated with no side effects * - repeated reads return the last value written @@ -407,6 +414,9 @@ void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size); #define ioremap_wc ioremap_wc #define ioremap_wt ioremap_wc +void __iomem *ioremap_nopost(resource_size_t res_cookie, size_t size); +#define ioremap_nopost ioremap_nopost + void iounmap(volatile void __iomem *iomem_cookie); #define iounmap iounmap diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index ff0eed2..4ffaf16 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c @@ -463,6 +463,13 @@ void iounmap(volatile void __iomem *cookie) } EXPORT_SYMBOL(iounmap); +void __iomem *ioremap_nopost(resource_size_t res_cookie, size_t size) +{ + return arch_ioremap_caller(res_cookie, size, MT_UNCACHED, + __builtin_return_address(0)); +} +EXPORT_SYMBOL_GPL(ioremap_nopost); + #ifdef CONFIG_PCI static int pci_ioremap_mem_type = MT_DEVICE; diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c index 3b5c7aa..dfd736a 100644 --- a/arch/arm/mm/nommu.c +++ b/arch/arm/mm/nommu.c @@ -21,6 +21,8 @@ #include #include +#include + #include "mm.h" unsigned long vectors_base; @@ -433,6 +435,13 @@ void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size) } EXPORT_SYMBOL(ioremap_wc); +void __iomem *ioremap_nopost(resource_size_t res_cookie, size_t size) +{ + return __arm_ioremap_caller(res_cookie, size, MT_UNCACHED, + __builtin_return_address(0)); +} +EXPORT_SYMBOL(ioremap_nopost); + void *arch_memremap_wb(phys_addr_t phys_addr, size_t size) { return (void *)phys_addr;