From patchwork Tue Apr 11 12:28:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Pieralisi X-Patchwork-Id: 9675079 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7101060234 for ; Tue, 11 Apr 2017 12:30:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 657E528384 for ; Tue, 11 Apr 2017 12:30:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5A6D32852D; Tue, 11 Apr 2017 12:30:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9F71F2852B for ; Tue, 11 Apr 2017 12:30:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754822AbdDKMaE (ORCPT ); Tue, 11 Apr 2017 08:30:04 -0400 Received: from foss.arm.com ([217.140.101.70]:59906 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754819AbdDKMaC (ORCPT ); Tue, 11 Apr 2017 08:30:02 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A06C31B2D; Tue, 11 Apr 2017 05:29:56 -0700 (PDT) Received: from red-moon.cambridge.arm.com (red-moon.cambridge.arm.com [10.1.206.55]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 79A443F23B; Tue, 11 Apr 2017 05:29:55 -0700 (PDT) From: Lorenzo Pieralisi To: linux-pci@vger.kernel.org Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Lorenzo Pieralisi , Bjorn Helgaas , Michal Simek Subject: [PATCH v3 15/32] microblaze: include default ioremap_nopost() implementation Date: Tue, 11 Apr 2017 13:28:55 +0100 Message-Id: <20170411122923.6285-16-lorenzo.pieralisi@arm.com> X-Mailer: git-send-email 2.10.0 In-Reply-To: <20170411122923.6285-1-lorenzo.pieralisi@arm.com> References: <20170411122923.6285-1-lorenzo.pieralisi@arm.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and Posting") mandate non-posted configuration transactions. As further highlighted in the PCIe specifications (4.0 - Rev0.3, "Ordering Considerations for the Enhanced Configuration Access Mechanism"), through ECAM and ECAM-derivative configuration mechanism, the memory mapped transactions from the host CPU into Configuration Requests on the PCI express fabric may create ordering problems for software because writes to memory address are typically posted transactions (unless the architecture can enforce through virtual address mapping non-posted write transactions behaviour) but writes to Configuration Space are not posted on the PCI express fabric. Include the asm-generic ioremap_nopost() implementation (currently falling back to ioremap_nocache()) to provide a non-posted writes ioremap interface to kernel subsystems. Signed-off-by: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Michal Simek --- arch/microblaze/include/asm/io.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h index 39b6315..4714a6d 100644 --- a/arch/microblaze/include/asm/io.h +++ b/arch/microblaze/include/asm/io.h @@ -43,6 +43,7 @@ extern void __iomem *ioremap(phys_addr_t address, unsigned long size); #define ioremap_fullcache(addr, size) ioremap((addr), (size)) #define ioremap_wc(addr, size) ioremap((addr), (size)) #define ioremap_wt(addr, size) ioremap((addr), (size)) +#include #endif /* CONFIG_MMU */