| Message ID | 20170411122923.6285-9-lorenzo.pieralisi@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
On Tue, Apr 11, 2017 at 01:28:48PM +0100, Lorenzo Pieralisi wrote: > The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and Posting") > mandate non-posted configuration transactions. As further highlighted in > the PCIe specifications (4.0 - Rev0.3, "Ordering Considerations for the > Enhanced Configuration Access Mechanism"), through ECAM and > ECAM-derivative configuration mechanism, the memory mapped transactions > from the host CPU into Configuration Requests on the PCI express fabric > may create ordering problems for software because writes to memory > address are typically posted transactions (unless the architecture can > enforce through virtual address mapping non-posted write transactions > behaviour) but writes to Configuration Space are not posted on the PCI > express fabric. > > Include the asm-generic ioremap_nopost() implementation (currently > falling back to ioremap_nocache()) to provide a non-posted writes > ioremap interface to kernel subsystems. > > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> > Cc: Niklas Cassel <nks@flawful.org> > Cc: Bjorn Helgaas <bhelgaas@google.com> For the CRIS-part: Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> /^JN - Jesper Nilsson
diff --git a/arch/cris/include/asm/io.h b/arch/cris/include/asm/io.h index fe0b2a0..b9c9397 100644 --- a/arch/cris/include/asm/io.h +++ b/arch/cris/include/asm/io.h @@ -21,5 +21,6 @@ extern void iounmap(volatile void * __iomem addr); extern void __iomem * ioremap_nocache(unsigned long offset, unsigned long size); #include <asm-generic/io.h> +#include <asm-generic/ioremap-nopost.h> #endif
The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and Posting") mandate non-posted configuration transactions. As further highlighted in the PCIe specifications (4.0 - Rev0.3, "Ordering Considerations for the Enhanced Configuration Access Mechanism"), through ECAM and ECAM-derivative configuration mechanism, the memory mapped transactions from the host CPU into Configuration Requests on the PCI express fabric may create ordering problems for software because writes to memory address are typically posted transactions (unless the architecture can enforce through virtual address mapping non-posted write transactions behaviour) but writes to Configuration Space are not posted on the PCI express fabric. Include the asm-generic ioremap_nopost() implementation (currently falling back to ioremap_nocache()) to provide a non-posted writes ioremap interface to kernel subsystems. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Niklas Cassel <nks@flawful.org> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Jesper Nilsson <jesper.nilsson@axis.com> Cc: Mikael Starvik <starvik@axis.com> --- arch/cris/include/asm/io.h | 1 + 1 file changed, 1 insertion(+)