From patchwork Wed Apr 19 16:48:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Pieralisi X-Patchwork-Id: 9688177 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B530E602DC for ; Wed, 19 Apr 2017 16:55:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A76D92842B for ; Wed, 19 Apr 2017 16:55:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9C25128433; Wed, 19 Apr 2017 16:55:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 45CC32842B for ; Wed, 19 Apr 2017 16:55:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966729AbdDSQt1 (ORCPT ); Wed, 19 Apr 2017 12:49:27 -0400 Received: from foss.arm.com ([217.140.101.70]:44124 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S938315AbdDSQtR (ORCPT ); Wed, 19 Apr 2017 12:49:17 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D663116A3; Wed, 19 Apr 2017 09:49:05 -0700 (PDT) Received: from red-moon.cambridge.arm.com (red-moon.cambridge.arm.com [10.1.206.55]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0CDFD3F4FF; Wed, 19 Apr 2017 09:49:00 -0700 (PDT) From: Lorenzo Pieralisi To: linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Lorenzo Pieralisi , Arnd Bergmann , Russell King , Will Deacon , Catalin Marinas , Benjamin Herrenschmidt , Pratyush Anand , Jingoo Han , Bjorn Helgaas , Mingkai Hu , John Garry , Tanmay Inamdar , Murali Karicheri , Bharat Kumar Gogada , Ray Jui , Wenrui Li , Shawn Lin , Minghuan Lian , Jon Mason , Gabriele Paoloni , Thomas Petazzoni , Joao Pinto , Thierry Reding , Michal Simek , Stanimir Varbanov , Zhou Wang , Roy Zang , "Luis R. Rodriguez" Subject: [PATCH v4 04/21] ARM: implement pci_remap_cfgspace() interface Date: Wed, 19 Apr 2017 17:48:53 +0100 Message-Id: <20170419164913.19674-5-lorenzo.pieralisi@arm.com> X-Mailer: git-send-email 2.10.0 In-Reply-To: <20170419164913.19674-1-lorenzo.pieralisi@arm.com> References: <20170419164913.19674-1-lorenzo.pieralisi@arm.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The PCI bus specifications (rev 3.0, 3.2.5 "Transaction Ordering and Posting") define rules for PCI configuration space transactions ordering and posting, that state that configuration writes have to be non-posted transactions. Current ioremap interface on ARM provides mapping functions that provide "bufferable" writes transactions (ie ioremap uses MT_DEVICE memory type) aka posted writes, so PCI host controller drivers have no arch interface to remap PCI configuration space with memory attributes that comply with the PCI specifications for configuration space. Implement an ARM specific pci_remap_cfgspace() interface that allows to map PCI config memory regions with MT_UNCACHED memory type (ie strongly ordered - non-posted writes), providing a remap function that complies with PCI specifications for config space transactions. Signed-off-by: Lorenzo Pieralisi Cc: Arnd Bergmann Cc: Russell King --- arch/arm/include/asm/io.h | 10 ++++++++++ arch/arm/mm/ioremap.c | 7 +++++++ arch/arm/mm/nommu.c | 12 ++++++++++++ 3 files changed, 29 insertions(+) diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 42871fb..74d1b09 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -187,6 +187,16 @@ static inline void pci_ioremap_set_mem_type(int mem_type) {} extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr); /* + * PCI configuration space mapping function. + * + * PCI specifications does not allow configuration write + * transactions to be posted. Add an arch specific + * pci_remap_cfgspace definition that is implemented + * through strongly ordered memory mappings. + */ +#define pci_remap_cfgspace pci_remap_cfgspace +void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size); +/* * Now, pick up the machine-defined IO definitions */ #ifdef CONFIG_NEED_MACH_IO_H diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index ff0eed2..fc91205 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c @@ -481,6 +481,13 @@ int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr) __pgprot(get_mem_type(pci_ioremap_mem_type)->prot_pte)); } EXPORT_SYMBOL_GPL(pci_ioremap_io); + +void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size) +{ + return arch_ioremap_caller(res_cookie, size, MT_UNCACHED, + __builtin_return_address(0)); +} +EXPORT_SYMBOL_GPL(pci_remap_cfgspace); #endif /* diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c index 33a45bd..3b8e728 100644 --- a/arch/arm/mm/nommu.c +++ b/arch/arm/mm/nommu.c @@ -436,6 +436,18 @@ void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size) } EXPORT_SYMBOL(ioremap_wc); +#ifdef CONFIG_PCI + +#include + +void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size) +{ + return arch_ioremap_caller(res_cookie, size, MT_UNCACHED, + __builtin_return_address(0)); +} +EXPORT_SYMBOL_GPL(pci_remap_cfgspace); +#endif + void *arch_memremap_wb(phys_addr_t phys_addr, size_t size) { return (void *)phys_addr;