[1/9] lspci: Decode AER Multiple Header and TLP Prefix Log bits

Message ID	20170421193133.6562.40599.stgit@bhelgaas-glaptop.roam.corp.google.com (mailing list archive)
State	New, archived
Delegated to:	Bjorn Helgaas
Headers	show Return-Path: <linux-pci-owner@kernel.org> Subject: [PATCH 1/9] lspci: Decode AER Multiple Header and TLP Prefix Log bits From: Bjorn Helgaas <helgaas@kernel.org> To: Martin Mares <mj@ucw.cz> Cc: linux-pci@vger.kernel.org, Jayachandran C <jnair@caviumnetworks.com> Date: Fri, 21 Apr 2017 14:31:33 -0500 Message-ID: <20170421193133.6562.40599.stgit@bhelgaas-glaptop.roam.corp.google.com> In-Reply-To: <20170421192844.6562.30976.stgit@bhelgaas-glaptop.roam.corp.google.com> References: <20170421192844.6562.30976.stgit@bhelgaas-glaptop.roam.corp.google.com> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Sender: linux-pci-owner@vger.kernel.org Precedence: bulk

diff --git a/lib/header.h b/lib/header.h index 6d81cb7..f031e37 100644 --- a/lib/header.h +++ b/lib/header.h @@ -958,6 +958,10 @@ #define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */ #define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */ #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */ +#define PCI_ERR_CAP_MULT_HDRC 0x00000200 /* Multiple Header Capable */ +#define PCI_ERR_CAP_MULT_HDRE 0x00000400 /* Multiple Header Enable */ +#define PCI_ERR_CAP_TLP_PFX 0x00000800 /* TLP Prefix Log Present */ +#define PCI_ERR_CAP_HDR_LOG 0x00001000 /* Completion Timeout Prefix/Header Log Capable */ #define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */ #define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */ #define PCI_ERR_ROOT_STATUS 48 diff --git a/ls-ecaps.c b/ls-ecaps.c index fdb98aa..ce3c613 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -131,10 +131,12 @@ cap_aer(struct device *d, int where) FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP), FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE)); l = get_conf_long(d, where + PCI_ERR_CAP); - printf("\t\tAERCap:\tFirst Error Pointer: %02x, GenCap%c CGenEn%c ChkCap%c ChkEn%c\n", + printf("\t\tAERCap:\tFirst Error Pointer: %02x, GenCap%c CGenEn%c ChkCap%c ChkEn%c\n" + "\t\t\tMultHdrRecCap%c MultHdrRecEn%c TLPPfxPres%c HdrLogCap%c\n", PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE), - FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE)); - + FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE), + FLAG(l, PCI_ERR_CAP_MULT_HDRC), FLAG(l, PCI_ERR_CAP_MULT_HDRE), + FLAG(l, PCI_ERR_CAP_TLP_PFX), FLAG(l, PCI_ERR_CAP_HDR_LOG)); } static void cap_dpc(struct device *d, int where) diff --git a/tests/cap-aer-hdr b/tests/cap-aer-hdr new file mode 100644 index 0000000..198f9dc --- /dev/null +++ b/tests/cap-aer-hdr @@ -0,0 +1,322 @@ +00:1c.0 PCI bridge: Intel Corporation Device 9d10 (rev f1) (prog-if 00 [Normal decode]) + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- + Latency: 0 + Interrupt: pin A routed to IRQ 255 + Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 + I/O behind bridge: None + Memory behind bridge: f1100000-f11fffff [size=1M] + Prefetchable memory behind bridge: None + Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- + BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00 + DevCap: MaxPayload 256 bytes, PhantFunc 0 + ExtTag- RBE+ + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 256 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- + LnkCap: Port #1, Speed 8GT/s, Width x1, ASPM L1, Exit Latency L0s <1us, L1 <16us + ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+ + LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk+ + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- + SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- + Slot #0, PowerLimit 10.000W; Interlock- NoCompl+ + SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- + Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- + SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- + Changed: MRL- PresDet- LinkState+ + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + DevCap2: Completion Timeout: Range ABC, TimeoutDis+, LTR+, OBFF Not Supported ARIFwd+ + AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS- + DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled ARIFwd- + AtomicOpsCtl: ReqEn- EgressBlck- + LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis- + Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- + Compliance De-emphasis: -6dB + LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1- + EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- + Capabilities: [80] MSI: Enable- Count=1/1 Maskable- 64bit- + Address: 00000000 Data: 0000 + Capabilities: [90] Subsystem: Lenovo Device 2238 + Capabilities: [a0] Power Management version 3 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Advanced Error Reporting + UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- + UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt+ RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- + UESvrt: DLP+ SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- + CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- + CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ + AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- + MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- + Capabilities: [140 v1] Access Control Services + ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd- EgressCtrl- DirectTrans- + ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- + Capabilities: [200 v1] L1 PM Substates + L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ + PortCommonModeRestoreTime=40us PortTPowerOnTime=10us + L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ + T_CommonMode=60us LTR1.2_Threshold=163840ns + L1SubCtl2: T_PwrOn=60us + Capabilities: [220 v1] #19 +00: 86 80 10 9d 07 00 10 00 f1 00 04 06 00 00 81 00 +10: 00 00 00 00 00 00 00 00 00 02 02 00 f0 00 00 20 +20: 10 f1 10 f1 f1 ff 01 00 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 01 00 00 +40: 10 80 42 01 01 80 00 00 20 00 10 00 13 48 72 01 +50: 42 00 12 70 00 b2 04 00 00 00 40 01 00 00 00 00 +60: 00 00 00 00 37 08 00 00 00 04 00 00 0e 00 00 00 +70: 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 05 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +90: 0d a0 00 00 aa 17 38 22 00 00 00 00 00 00 00 00 +a0: 01 00 03 c8 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 11 10 00 07 42 18 00 00 08 00 9e 8b 00 00 00 00 +e0: 00 f7 f3 00 00 00 00 00 06 80 12 00 00 00 00 00 +f0: 50 01 00 00 00 03 00 40 b3 0f 30 08 04 00 00 01 +100: 01 00 01 14 00 00 00 00 00 00 01 00 11 00 06 00 +110: 00 00 00 00 00 20 00 00 00 00 00 00 00 00 00 00 +120: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +130: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +140: 0d 00 01 20 0f 00 00 00 00 00 00 00 00 00 00 00 +150: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +160: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +170: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +180: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +190: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +1a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +1b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +1c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +1d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +1e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +1f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +200: 1e 00 01 22 1f 28 28 00 0f 3c a0 40 31 00 00 00 +210: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +220: 19 00 01 00 00 00 00 00 00 00 00 00 77 75 77 75 +230: 77 75 77 75 00 00 00 00 00 00 00 00 00 00 00 00 +240: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +250: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +260: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +270: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +280: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +290: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +2a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +2b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +2c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +2d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +2e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +2f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +300: a7 5f b7 00 97 0c c0 1b 00 00 00 00 00 00 00 00 +310: 00 00 00 00 38 3f 70 7e 00 00 14 14 d9 23 6a 05 +320: db 60 d9 69 20 60 00 08 4f 19 18 3c 4e 99 85 08 +330: 16 00 00 2a bc b5 bc 4a 72 01 00 30 00 00 00 00 +340: d8 00 d8 00 f8 00 dc 00 5e 00 1a 00 4e 00 69 00 +350: 52 00 6d 00 01 00 1a 00 18 00 0e 00 00 00 00 00 +360: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +370: 00 00 00 00 00 00 00 00 00 00 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[1/9] lspci: Decode AER Multiple Header and TLP Prefix Log bits

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