| Message ID | 20170426111809.19922-8-lorenzo.pieralisi@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
On Wed, Apr 26, 2017 at 12:17:58PM +0100, Lorenzo Pieralisi wrote: > The introduction of pci_scan_root_bus_bridge() provides a PCI core > API to scan a PCI root bus backed by an already initialized > struct pci_host_bridge object, which simplifies the bus scan > interface and makes the PCI scan root bus interface easier to > generalize as members are added to the struct pci_host_bridge(). > > Convert ARM orion5x platform code to pci_scan_root_bus_bridge() to > improve the PCI root bus scanning interface. Hi Lorenzo Maybe there is something not right here. With plain 4.11-rc7 i get: root@orion5x:~# lspci -v 0000:00:00.0 Memory controller: Marvell Technology Group Ltd. 88f5182 [Orion-NAS] ARM SoC (rev 02) Subsystem: Marvell Technology Group Ltd. Device 11ab Flags: bus master, fast devsel, latency 0, IRQ 12 Memory at <ignored> (64-bit, prefetchable) Capabilities: [40] Power Management version 2 Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Capabilities: [60] Express Root Port (Slot-), MSI 00 0001:01:00.0 Memory controller: Marvell Technology Group Ltd. 88f5182 [Orion-NAS] ARM SoC (rev 02) Flags: bus master, fast Back2Back, 66MHz, medium devsel, latency 0 BIST result: 00 Memory at <unassigned> (64-bit, prefetchable) Memory at <ignored> (64-bit, prefetchable) Memory at <ignored> (64-bit, non-prefetchable) Expansion ROM at <ignored> [disabled] Capabilities: [40] Power Management version 2 Capabilities: [48] Vital Product Data Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Capabilities: [60] PCI-X non-bridge device Capabilities: [68] CompactPCI hot-swap <?> However, with your patches applied i get: 0000:00:00.0 Memory controller: Marvell Technology Group Ltd. 88f5182 [Orion-NAS] ARM SoC (rev 02) Subsystem: Marvell Technology Group Ltd. Device 11ab Flags: bus master, fast devsel, latency 0 Memory at <ignored> (64-bit, prefetchable) Capabilities: [40] Power Management version 2 Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Capabilities: [60] Express Root Port (Slot-), MSI 00 0001:01:00.0 Memory controller: Marvell Technology Group Ltd. 88f5182 [Orion-NAS] ARM SoC (rev 02) Flags: bus master, fast Back2Back, 66MHz, medium devsel, latency 0 BIST result: 00 Memory at <unassigned> (64-bit, prefetchable) Memory at <ignored> (64-bit, prefetchable) Memory at <ignored> (64-bit, non-prefetchable) Expansion ROM at <ignored> [disabled] Capabilities: [40] Power Management version 2 Capabilities: [48] Vital Product Data Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Capabilities: [60] PCI-X non-bridge device Capabilities: [68] CompactPCI hot-swap <?> Note that IRQ 12 has disappeared from Flags: on 0000:00:00.0. Since there are no actual PCI devices on this bus, i cannot test if interrupts are broken. Andrew
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index ecb998e..6dc4c89 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -557,13 +557,30 @@ int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys) struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) { - if (nr == 0) - return pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys, - &sys->resources); + struct pci_host_bridge *bridge; + int ret = -ENODEV; - if (nr == 1 && !orion5x_pci_disabled) - return pci_scan_root_bus(NULL, sys->busnr, &pci_ops, sys, - &sys->resources); + bridge = pci_alloc_host_bridge(0); + if (!bridge) + return NULL; + + list_splice_init(&sys->resources, &bridge->windows); + bridge->dev.parent = NULL; + bridge->sysdata = sys; + bridge->busnr = sys->busnr; + + if (nr == 0) { + bridge->ops = &pcie_ops; + ret = pci_scan_root_bus_bridge(bridge); + } + + if (nr == 1 && !orion5x_pci_disabled) { + bridge->ops = &pci_ops; + ret = pci_scan_root_bus_bridge(bridge); + } + + if (!ret) + return bridge->bus; BUG(); return NULL;
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to scan a PCI root bus backed by an already initialized struct pci_host_bridge object, which simplifies the bus scan interface and makes the PCI scan root bus interface easier to generalize as members are added to the struct pci_host_bridge(). Convert ARM orion5x platform code to pci_scan_root_bus_bridge() to improve the PCI root bus scanning interface. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Andrew Lunn <andrew@lunn.ch> --- arch/arm/mach-orion5x/pci.c | 29 +++++++++++++++++++++++------ 1 file changed, 23 insertions(+), 6 deletions(-)