From patchwork Tue May 23 19:42:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 9743249 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E0C8B6032B for ; Tue, 23 May 2017 19:42:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D277928809 for ; Tue, 23 May 2017 19:42:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C6AB12880D; Tue, 23 May 2017 19:42:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6A29928809 for ; Tue, 23 May 2017 19:42:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759816AbdEWTme (ORCPT ); Tue, 23 May 2017 15:42:34 -0400 Received: from mail.kernel.org ([198.145.29.99]:40706 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751722AbdEWTme (ORCPT ); Tue, 23 May 2017 15:42:34 -0400 Received: from localhost (unknown [69.55.156.165]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 652552395D; Tue, 23 May 2017 19:42:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 652552395D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=helgaas@kernel.org Date: Tue, 23 May 2017 14:42:32 -0500 From: Bjorn Helgaas To: Shawn Lin Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, Brian Norris , Jeffy Chen Subject: Re: [PATCH] PCI: rockchip: Configure RC's MPS setting Message-ID: <20170523194232.GC7241@bhelgaas-glaptop.roam.corp.google.com> References: <1493887204-5501-1-git-send-email-shawn.lin@rock-chips.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1493887204-5501-1-git-send-email-shawn.lin@rock-chips.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Thu, May 04, 2017 at 04:40:04PM +0800, Shawn Lin wrote: > The default value of MPS for RC is 128 bytes, but actually > it could support 256 bytes. So this patch fix this issue. > > Signed-off-by: Shawn Lin Applied to pci/host-rockchip for v4.13, thanks! This didn't apply cleanly on top of the previous restructuring patches, so I'm attaching the patch as applied. Let me know if you want the MPS setting with the PCIE_RC_BAR_CONF instead of with the PCIE_RC_CONFIG_LINK_CAP. commit 60f8ed61a6bc729ba3367e6f1a2dd3a80c94cd73 Author: Shawn Lin Date: Tue May 23 14:32:56 2017 -0500 PCI: rockchip: Configure RC's MPS setting The default value of MPS for RC is 128 bytes, but actually it could support 256 bytes. So this patch fixes this issue. Signed-off-by: Shawn Lin Signed-off-by: Bjorn Helgaas > --- > > drivers/pci/host/pcie-rockchip.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c > index 0e020b6..a05fec5 100644 > --- a/drivers/pci/host/pcie-rockchip.c > +++ b/drivers/pci/host/pcie-rockchip.c > @@ -146,6 +146,9 @@ > #define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18 > #define PCIE_RC_CONFIG_DCR_CSPL_LIMIT 0xff > #define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26 > +#define PCIE_RC_CONFIG_DCSR (PCIE_RC_CONFIG_BASE + 0xc8) > +#define PCIE_RC_CONFIG_DCSR_MPS_MASK GENMASK(7, 5) > +#define PCIE_RC_CONFIG_DCSR_MPS_256 (0x1 << 5) > #define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc) > #define PCIE_RC_CONFIG_LINK_CAP_L0S BIT(10) > #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0) > @@ -664,6 +667,11 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) > rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP); > } > > + status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCSR); > + status &= ~PCIE_RC_CONFIG_DCSR_MPS_MASK; > + status |= PCIE_RC_CONFIG_DCSR_MPS_256; > + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCSR); > + > rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF); > > rockchip_pcie_write(rockchip, > -- > 1.9.1 > > diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c index bf0ff579e515..2e832b1d6c24 100644 --- a/drivers/pci/host/pcie-rockchip.c +++ b/drivers/pci/host/pcie-rockchip.c @@ -146,6 +146,9 @@ #define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18 #define PCIE_RC_CONFIG_DCR_CSPL_LIMIT 0xff #define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26 +#define PCIE_RC_CONFIG_DCSR (PCIE_RC_CONFIG_BASE + 0xc8) +#define PCIE_RC_CONFIG_DCSR_MPS_MASK GENMASK(7, 5) +#define PCIE_RC_CONFIG_DCSR_MPS_256 (0x1 << 5) #define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc) #define PCIE_RC_CONFIG_LINK_CAP_L0S BIT(10) #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0) @@ -701,6 +704,11 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP); } + status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCSR); + status &= ~PCIE_RC_CONFIG_DCSR_MPS_MASK; + status |= PCIE_RC_CONFIG_DCSR_MPS_256; + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCSR); + return 0; }