From patchwork Thu Jun 8 14:13:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Pieralisi X-Patchwork-Id: 9775527 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 240A160350 for ; Thu, 8 Jun 2017 14:14:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1543F20855 for ; Thu, 8 Jun 2017 14:14:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 09ACB2855A; Thu, 8 Jun 2017 14:14:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7D5C320855 for ; Thu, 8 Jun 2017 14:14:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751545AbdFHOOT (ORCPT ); Thu, 8 Jun 2017 10:14:19 -0400 Received: from foss.arm.com ([217.140.101.70]:50804 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751518AbdFHOOT (ORCPT ); Thu, 8 Jun 2017 10:14:19 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9F399168F; Thu, 8 Jun 2017 07:14:18 -0700 (PDT) Received: from red-moon.cambridge.arm.com (red-moon.cambridge.arm.com [10.1.206.55]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 23FFE3F3E1; Thu, 8 Jun 2017 07:14:13 -0700 (PDT) From: Lorenzo Pieralisi To: linux-pci@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Lorenzo Pieralisi , Bjorn Helgaas , Bharat Kumar Gogada , Arnd Bergmann , Will Deacon , Russell King , Pratyush Anand , Jingoo Han , Rob Herring , Simon Horman , Mingkai Hu , Tanmay Inamdar , Murali Karicheri , Wenrui Li , Shawn Lin , Minghuan Lian , Gabriele Paoloni , Thomas Petazzoni , Joao Pinto , Thierry Reding , Michal Simek , Stanimir Varbanov , Zhou Wang , Roy Zang , Matthew Minter , Linus Walleij Subject: [RFT PATCH v2 22/42] PCI: xilinx-nwl: Convert PCI scan API to pci_scan_root_bus_bridge() Date: Thu, 8 Jun 2017 15:13:22 +0100 Message-Id: <20170608141342.2018-23-lorenzo.pieralisi@arm.com> X-Mailer: git-send-email 2.10.0 In-Reply-To: <20170608141342.2018-1-lorenzo.pieralisi@arm.com> References: <20170608141342.2018-1-lorenzo.pieralisi@arm.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The introduction of pci_scan_root_bus_bridge() provides a PCI core API to scan a PCI root bus backed by an already initialized struct pci_host_bridge object, which simplifies the bus scan interface and makes the PCI scan root bus interface easier to generalize as members are added to the struct pci_host_bridge. Convert PCI xilinx-nwl host code to pci_scan_root_bus_bridge() to improve the PCI root bus scanning interface. Signed-off-by: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Bharat Kumar Gogada --- drivers/pci/host/pcie-xilinx-nwl.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c index 26e66e8..e8a5894 100644 --- a/drivers/pci/host/pcie-xilinx-nwl.c +++ b/drivers/pci/host/pcie-xilinx-nwl.c @@ -791,13 +791,16 @@ static int nwl_pcie_probe(struct platform_device *pdev) struct nwl_pcie *pcie; struct pci_bus *bus; struct pci_bus *child; + struct pci_host_bridge *bridge; int err; resource_size_t iobase = 0; LIST_HEAD(res); - pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); - if (!pcie) - return -ENOMEM; + bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); + if (!bridge) + return -ENODEV; + + pcie = pci_host_bridge_priv(bridge); pcie->dev = dev; pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT; @@ -830,12 +833,11 @@ static int nwl_pcie_probe(struct platform_device *pdev) goto error; } - bus = pci_create_root_bus(dev, pcie->root_busno, - &nwl_pcie_ops, pcie, &res); - if (!bus) { - err = -ENOMEM; - goto error; - } + list_splice_init(&res, &bridge->windows); + bridge->dev.parent = dev; + bridge->sysdata = pcie; + bridge->busnr = pcie->root_busno; + bridge->ops = &nwl_pcie_ops; if (IS_ENABLED(CONFIG_PCI_MSI)) { err = nwl_pcie_enable_msi(pcie); @@ -844,7 +846,13 @@ static int nwl_pcie_probe(struct platform_device *pdev) goto error; } } - pci_scan_child_bus(bus); + + err = pci_scan_root_bus_bridge(bridge); + if (err) + goto error; + + bus = bridge->bus; + pci_assign_unassigned_bus_resources(bus); list_for_each_entry(child, &bus->children, node) pcie_bus_configure_settings(child);