From patchwork Wed Jun 14 08:23:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 9785955 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0091A60384 for ; Wed, 14 Jun 2017 09:52:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C863B205AB for ; Wed, 14 Jun 2017 09:52:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BD081285E3; Wed, 14 Jun 2017 09:52:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 75904205AB for ; Wed, 14 Jun 2017 09:52:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754697AbdFNIZT (ORCPT ); Wed, 14 Jun 2017 04:25:19 -0400 Received: from mail-pg0-f54.google.com ([74.125.83.54]:36488 "EHLO mail-pg0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754670AbdFNIZN (ORCPT ); Wed, 14 Jun 2017 04:25:13 -0400 Received: by mail-pg0-f54.google.com with SMTP id a70so72554790pge.3 for ; Wed, 14 Jun 2017 01:25:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=26ibPGtf3Fi4tY1hrxAlJrJuKlENMe8/xmgbIZrOl3w=; b=c6k8/+VWrAMsAAaJTC+ki/2mZKyFh7JHSglprk24oHsZDDMvDcjuYpWLNhFRtzlKRC 1CERX4wK7VNiYmAUZO/33VQNSTCS2JREyMW019SknfpPhkunDL6ol27TWiBCfYGWYdCi W/L/kTuhzegou/d0MJmnw+ZbslLdV34jjzZuA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=26ibPGtf3Fi4tY1hrxAlJrJuKlENMe8/xmgbIZrOl3w=; b=ZIFpddyixnuIK99xS6JmxjQBwRijJP/H573ase6xjUevQPAxWWoPVdcxqB2ZS8ZkEK avIUnVtrU60FcmfzqrL1aje/nZgWpSe855QvfjEj7wYJQRvEINXsnTOda6w7XYHOQXVN 4LkpB3cwKFxZigekkTkOhVQMH/sdLfuCXC5ddbhYroLN6imyYFMdtrOmMAf3e1WQ/1qp ZTAlCelO7KVdsI9+nfe+odlFJHI7aiYnkg6tydALfn5Kf42nhuoY/g8Cx4dpA5n6jxbO Qa32hD2UUO4lYRYIIc5Ha4rtXWf//e1huCPCc0FDbo27WVqd7QjU4M53L5br4QgzUVE5 P+sw== X-Gm-Message-State: AKS2vOwmtO6x187IkQWE5JAoS8+22V/4BSEJWS9Z5OjsX09nrnxiQ1JU V96HdlwbiJWRN8BU X-Received: by 10.98.50.129 with SMTP id y123mr3000516pfy.53.1497428713240; Wed, 14 Jun 2017 01:25:13 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.99]) by smtp.gmail.com with ESMTPSA id h14sm766802pfh.71.2017.06.14.01.25.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 01:25:12 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, xuejiancheng@hisilicon.com, peter.griffin@linaro.org, puck.chen@hisilicon.com, lee.jones@linaro.org, ulf.hansson@linaro.org, bhelgaas@google.com, arnd@arndb.de Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-pci@vger.kernel.org, Leo Yan Subject: [PATCH v3 13/21] arm64: dts: hi3660: add sp804 timer node Date: Wed, 14 Jun 2017 16:23:30 +0800 Message-Id: <20170614082338.15673-14-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170614082338.15673-1-guodong.xu@linaro.org> References: <20170614082338.15673-1-guodong.xu@linaro.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Leo Yan The Hi3660 SoC comes with the sp804 timer in addition to the architecture timers. These ones are shutdown when reaching a deep idle states and a backup timer is needed. The sp804 belongs to another power domain and can fulfill the purpose of replacing temporarily an architecture timer when the CPU is idle. Describe it in the device tree, so it can be enabled at boot time. Suggested-by: Daniel Lezcano Acked-by: Daniel Lezcano Signed-off-by: Leo Yan --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index a6b91f1..e138973 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -186,6 +186,17 @@ #reset-cells = <2>; }; + dual_timer0: timer@fff14000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x0 0xfff14000 0x0 0x1000>; + interrupts = , + ; + clocks = <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + i2c0: i2c@ffd71000 { compatible = "snps,designware-i2c"; reg = <0x0 0xffd71000 0x0 0x1000>;