From patchwork Tue Oct 24 08:30:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaowei Bao X-Patchwork-Id: 10023723 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4C7C4604D7 for ; Tue, 24 Oct 2017 08:49:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3BA5528988 for ; Tue, 24 Oct 2017 08:49:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 302EC289B1; Tue, 24 Oct 2017 08:49:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AF67228988 for ; Tue, 24 Oct 2017 08:49:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932414AbdJXIt1 (ORCPT ); Tue, 24 Oct 2017 04:49:27 -0400 Received: from mail-by2nam03on0085.outbound.protection.outlook.com ([104.47.42.85]:24064 "EHLO NAM03-BY2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932458AbdJXItM (ORCPT ); Tue, 24 Oct 2017 04:49:12 -0400 Received: from BN3PR03CA0082.namprd03.prod.outlook.com (10.167.1.170) by BN6PR03MB2692.namprd03.prod.outlook.com (10.173.144.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.178.6; Tue, 24 Oct 2017 08:49:09 +0000 Received: from BY2FFO11FD032.protection.gbl (2a01:111:f400:7c0c::125) by BN3PR03CA0082.outlook.office365.com (2a01:111:e400:7a4d::42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.178.6 via Frontend Transport; Tue, 24 Oct 2017 08:49:09 +0000 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed) header.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com; Received-SPF: Fail (protection.outlook.com: domain of nxp.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Received: from tx30smr01.am.freescale.net (192.88.168.50) by BY2FFO11FD032.mail.protection.outlook.com (10.1.14.210) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.20.156.4 via Frontend Transport; Tue, 24 Oct 2017 08:49:08 +0000 Received: from titan.ap.freescale.net ([10.192.208.233]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id v9O8mfxd031253; Tue, 24 Oct 2017 01:49:01 -0700 From: Bao Xiaowei To: , , , , , , , , , , , , , , , , , , , , , , , CC: Bao Xiaowei Subject: [PATCH 2/3] ARMv8: layerscape: add the pcie ep function support Date: Tue, 24 Oct 2017 16:30:44 +0800 Message-ID: <20171024083045.31135-3-xiaowei.bao@nxp.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171024083045.31135-1-xiaowei.bao@nxp.com> References: <20171024083045.31135-1-xiaowei.bao@nxp.com> X-EOPAttributedMessage: 0 X-Matching-Connectors: 131533085493312775; (91ab9b29-cfa4-454e-5278-08d120cd25b8); () X-Forefront-Antispam-Report: CIP:192.88.168.50; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(336005)(39860400002)(39380400002)(376002)(346002)(2980300002)(1109001)(1110001)(339900001)(199003)(189002)(77096006)(2201001)(86362001)(53936002)(356003)(81156014)(39060400002)(6636002)(97736004)(106466001)(6666003)(8656005)(8656005)(5660300001)(110136005)(33646002)(7416002)(85426001)(16586007)(105606002)(2950100002)(5003940100001)(76176999)(1076002)(50986999)(498600001)(316002)(47776003)(104016004)(189998001)(81166006)(68736007)(50226002)(8676002)(48376002)(305945005)(50466002)(8936002)(2906002)(36756003)(4326008)(921003)(1121003)(83996005)(2101003); DIR:OUT; SFP:1101; SCL:1; SRVR:BN6PR03MB2692; H:tx30smr01.am.freescale.net; FPR:; SPF:Fail; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; X-Microsoft-Exchange-Diagnostics: 1; BY2FFO11FD032; 1:BkneR2udeawC9msHjobFG9fNo0ez0CcxXZziyg1Wbp79ftiHkLVUrcJ5HlMcrnv9ke64msIUHKWbaUog3PHwDtBe9ECUlCChdKHXMRDLfPE2SortvcSHjzi4m4JjtuTu MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0a342a16-fbe4-4158-3207-08d51abc176e X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(4534020)(4628075)(201703131517081)(2017052603199); SRVR:BN6PR03MB2692; X-Microsoft-Exchange-Diagnostics: 1; BN6PR03MB2692; 3:rcVKIf/nMhyL2liTMqEQs0DXuw3LMygufcY6Ge69YlQUVrYh9ftpDo79ITuFluTa+Nsihkn4i1HA9uJ6AzwEOIQN+P1G1KgbngJnzDs6DMJFxGYhO15X2kas0AwZeYQshjpYhPgWzBn+HnkONAAmfURyVPZslh419Zch29iDsMLAlRseePLk8rXrWicHHIWS4Ngmngpxjyt1tpSCTL7heCW/Oi3/oTfzSWy26yZFSf5+BMkmKvbeyDvYBbBDcOvUTTwkypILuqhL81cqu6sOoTENVPfVY8ZjdsmMt15dAe7D+EUBykuuhCeDGhEosZcR3BX73ffetiNugs56Y++uLknYIIoku5qnhvYrRLYcJMs=; 25:E50Xo2g/rV+/DnYefy4WwEm+Usu1UrWuJWkD5RxxA51omPA8DFKLKjO3/y1lpIzo8u8QvlOsetieDXZcjxG6GSzhO/CabOnQLBMHKwyUvlC/UEb4K6FoXPppEzilDzWy/6ypOdujD0KVaekRC8viZ+4vG43OsDCcokZaBk+TCyqgA3LfXKKXovjxW3GUq+VRIWBauD5F+rRE79BuD2wqfOlChFJBDi4tcxtvICMnpBApQZCNUyiRqgFWz4g5dL24yUiGdZlHNv3kFUh4cgK/7Jrs8mbkqivhpJoFiGymoHxzjDouz4G+O1gSfEsyxEdTG3ZhE+pD3KTbSu6zNKevqg== X-MS-TrafficTypeDiagnostic: BN6PR03MB2692: X-Microsoft-Exchange-Diagnostics: 1; BN6PR03MB2692; 31:FhTQRCf/rldMBR6ueFEi8IfecRuXh/6Rps0BPp3/NO8TIulCZNNC6Ou7aFAhRuprM5iVH2/uqnJsLqnx/LRbFg7saglzH2kMkaPEWuZiSU4Y9hQdkXJ3/u9uneWpR7r6FEnHWHcthir949RjxJj6rhaPXFq9FvKLfURNJ3cT8m4yvo7mJl70rXssT7I35ESRyilZlJCFKoC4bzeh693L4Q8r7BMaJtLHFerl1iIkSO4=; 4:kHCAkBkOa0e0abWiNnnAGo8rPnV9sqPqKVEoFWQr/R4KBluYJpGgno7biVbpISeKGanjCDp41XkU+r9yvJc3gH+zgyFm2+t5ozhlrB/KubUUwq3lnyR/UTJt9zjFequ0Ex0Q6pw7V5pHLR5/HnqYKNqhfLp2jjgPLSvSKM0gYSfBLsQe/S0AXpW8PahklNFE9Fvm+1ocaJ7Kz+l7NuwhKUXVje3M2eYbpnutR5yC8PT4rLFIe1hyxm3IgHJHWOQ8Bkj38B6X8tdnBVNAmoFFfIEUInlCwJ0/397vOnFwQleEKlQH2kBlS7LxPIRDy2YZ X-Exchange-Antispam-Report-Test: UriScan:(185117386973197); X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6095135)(2401047)(5005006)(8121501046)(10201501046)(3002001)(3231020)(100000703101)(100105400095)(93006095)(93001095)(6055026)(6096035)(20161123559100)(20161123556025)(201703131430075)(201703131433075)(201703131448075)(201703161259150)(201703151042153)(20161123565025)(20161123561025)(20161123563025)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095); SRVR:BN6PR03MB2692; BCL:0; PCL:0; RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095); SRVR:BN6PR03MB2692; X-Forefront-PRVS: 047001DADA X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BN6PR03MB2692; 23:4vFXcmExRYJZa3Xv/bhWr3/X8UR3Zh0PDG6GL+UNX?= =?us-ascii?Q?OHdmWu0iwyMG0rae0WzBiixp/xuUVb9IausuyYS1sII8WAEBDJxDzUJWKkN2?= =?us-ascii?Q?ooeF1yIlyyk3GNOA3qqcQTClZfqMbYjNcrzOOaAqMq4VudghDWOgserpsbaD?= =?us-ascii?Q?QM65NHGu2xFY5aD21csP/gQKv20M7whkP8GlPrtFgum8VEEIxCO4AT6wmDOn?= =?us-ascii?Q?p41dfRi+Xqr15UhUgrzc0iqmN9AhL+Vp91Bjdjt+RSl/+m+K17zXlAn4154L?= =?us-ascii?Q?B3qRzgtfkVHqYKY52LLW/avuBgLxoS/gSAVDoZHrJSPLntUaG6nr8z0hWCUW?= =?us-ascii?Q?vaoeXnp3R06QVEBJn1zbIkm6VSIPndTE2dVNaQlQ+XEoveLv8EYvkbuHm35+?= =?us-ascii?Q?MbNjsGxARvr8smMZzYuPBXhOoPHSSRy8qRAWFPZhMoSW54zEinFH47b3YLsO?= =?us-ascii?Q?Q6SKFJYmnxSM8WbfOVx4+sMAIvlM05VRW+n7kBvhcPwebyUbv5Mvkm7tz4x0?= =?us-ascii?Q?3oH2s/Bg3LArlYlHo1Q7wn+LWYnDFHMCND60e8Tstlon4Bd4wnbPZKftFSX1?= =?us-ascii?Q?Zykuf7ZkXOhvDtRtgGIXrvQ4rijsReuG4xtzVZxOhlLey6qytLCKYnXZXOSO?= =?us-ascii?Q?kItAJ0oUmUuzSLLJa5JDuwIuiANeKCUFijT1f+BoaPtUWdhDxEsjPdWbEa24?= =?us-ascii?Q?E/jet7gyojmnXoGtqPpq/GJrm5JXlw1hKQWPUDabY6LA6dTrivVh50ZAxKE/?= =?us-ascii?Q?YM8veZXvOeNGSpuLzg2stNvrR7xt3e1lKD3n6VOqzxDsBZsDob4wqI2ZxZ3F?= =?us-ascii?Q?vFCo7ZIIOknjqW6ADladFe//iendICrJkxgD0ONRCa9CbfuW4mKTIQb7IG8g?= =?us-ascii?Q?BH4Zv7q+/yS7GRDR3Y4LoiB+tjr6U93g5Xi4Qwn36DZFX3bEovWUgDSR0lv9?= =?us-ascii?Q?qJrXCkjtgR9Ss+CrxRZvMKlJgGTfsciZlmkw2grfrkZN7jR6d0/7X/dYLTp8?= =?us-ascii?Q?3SgdYyXL3HOA6b5piP/nKxlZXco1rQqqt6dxvOd63WyPp+l6+j4GRs6DZLL/?= =?us-ascii?Q?7QirWkJWX42fHK10V8KBvvcGmxZAJ43gxEBtpTgh+TH/70UaSj+BzI3fH1nj?= =?us-ascii?Q?71UIV90v8MSobvwx8hgczRN3Nchj793lUcSMI8XYPEdUcBRAP+9ko3GNmk0a?= =?us-ascii?Q?zGQ9KLEHymuvw2btPEsCtSmkjO4VzhAnpXts6VDUqAme7fkGylfClX4ziKVt?= =?us-ascii?Q?dqGWoULeAfa6obRKVMIwBXHM/7pSKHNeVwkO1QYCUfAgls2crYEB5F8iKTVR?= =?us-ascii?Q?X4q+ZN2c5sMGFjS6KOSphE=3D?= X-Microsoft-Exchange-Diagnostics: 1; BN6PR03MB2692; 6:TNnIvKVxYJTqMeiQRuM0TSjNvMQ2DsIkHyYxx43BMM5QVJmk2yrq+PeZ02pFZfQsLLeve6sCz04nAEZP6NC32h3NdJJa4CwiFk9VksLhf3R0xN9ODfyc2QIySEc7WVIcub76aWz2uh3FQOXiThD8wpwaohci6fk0qzBbVOK+hwvoLM/jy5aXxhNQGENnBnW80P+4u00dlBcjKmkZPKmpD1OxF1efZJeX/yGSz7N7Gia+RAfwwV4+Zc8JR6u6QTWyQxPTVUTU0apMJdNgvfIG7dQWZGc1BQ/oQro+QwRkmWnKit0y6erdR+5N1V/dCuv+dPq/0sEgnlO2oKaisj/XzRVnyI8/vwfAmVaCgPWtpEo=; 5:UzAm/ZavfdRYhndFesehH4XctYmtcW8JbqxK4sWcgsRouTdu1F4jE8nX8F1mHhSwRcrDjPLksOBSs6MhCGMWinRWzytPljh8uAbpBUANewj7H5gQVPkXBkqTvguCECpWKkq2eIQNvmQltWErt+5qQ8M1GTK7drWrxDJr1qgsoZQ=; 24:5jn2lbDD84eSQe6nkq2pgRiZl6C4TKpfsFGWLQkzuHdAXOgySTqxkoQw9F185W99ufDFHlHmRETI7zZ/pmkAOXpq49Kts/j+hr64Ce3Wd78=; 7:6o3OWclT2LiRhesZCxAOW64W0h1yUOCGay8vgGkGJWczbyqRsBTKJmyF3M3Gti2ue94ALl8H4+mzffs/UyQzQXyD4vD4KTIM3HL3t+TgulMiu+x15kH7adK5wnaDZM2QkHdHJFK68iuRfSjv8gVZzXv9lw+ReCCHg2rMhIkeYa+wt422hkyBil31XJqfJSRXI3u5/Yz8lFp4i/g0sKxsJFuaJcerEC7Mj/fo5DQCJvxu6Thv1AU5V2kTiGxo/nvc SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2017 08:49:08.9568 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0a342a16-fbe4-4158-3207-08d51abc176e X-MS-Exchange-CrossTenant-Id: 5afe0b00-7697-4969-b663-5eab37d5f47e X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e; Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR03MB2692 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the pcie controller ep function support of layerscape base on pcie ep framework. Signed-off-by: Bao Xiaowei --- drivers/pci/dwc/pci-layerscape.c | 137 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 131 insertions(+), 6 deletions(-) diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c index 87fa486bee2c..5c6fa7534a8e 100644 --- a/drivers/pci/dwc/pci-layerscape.c +++ b/drivers/pci/dwc/pci-layerscape.c @@ -34,7 +34,12 @@ /* PEX Internal Configuration Registers */ #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */ +#define PCIE_DBI2_BASE 0x1000 /* DBI2 base address*/ +#define PCIE_MSI_MSG_DATA_OFF 0x5c /* MSI Data register address*/ +#define PCIE_MSI_OB_SIZE 4096 +#define PCIE_MSI_ADDR_OFFSET (1024 * 1024) #define PCIE_IATU_NUM 6 +#define PCIE_EP_ADDR_SPACE_SIZE 0x100000000 struct ls_pcie_drvdata { u32 lut_offset; @@ -44,12 +49,20 @@ struct ls_pcie_drvdata { const struct dw_pcie_ops *dw_pcie_ops; }; +struct ls_pcie_ep { + dma_addr_t msi_phys_addr; + void __iomem *msi_virt_addr; + u64 msi_msg_addr; + u16 msi_msg_data; +}; + struct ls_pcie { struct dw_pcie *pci; void __iomem *lut; struct regmap *scfg; const struct ls_pcie_drvdata *drvdata; int index; + struct ls_pcie_ep *pcie_ep; }; #define to_ls_pcie(x) dev_get_drvdata((x)->dev) @@ -263,6 +276,113 @@ static const struct of_device_id ls_pcie_of_match[] = { { }, }; +static void ls_pcie_raise_msi_irq(struct ls_pcie_ep *pcie_ep) +{ + iowrite32(pcie_ep->msi_msg_data, pcie_ep->msi_virt_addr); +} + +static void ls_pcie_ep_msi_init(struct dw_pcie_ep *ep) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + struct ls_pcie *pcie = to_ls_pcie(pci); + struct ls_pcie_ep *pcie_ep = pcie->pcie_ep; + struct device *dev = pci->dev; + u32 free_win; + + pcie_ep->msi_phys_addr = ep->phys_base + PCIE_MSI_ADDR_OFFSET; + + pcie_ep->msi_virt_addr = ioremap(pcie_ep->msi_phys_addr, + PCIE_MSI_OB_SIZE); + if (!pcie_ep->msi_virt_addr) + dev_err(dev, "failed to map MSI outbound region\n"); + + pcie_ep->msi_msg_addr = ioread32(pci->dbi_base + MSI_MESSAGE_ADDR_L32) | + (((u64)ioread32(pci->dbi_base + MSI_MESSAGE_ADDR_U32)) << 32); + pcie_ep->msi_msg_data = ioread16(pci->dbi_base + PCIE_MSI_MSG_DATA_OFF); + + /* outbound iATU for MSI */ + free_win = find_first_zero_bit(&ep->ob_window_map, + sizeof(ep->ob_window_map)); + if (free_win >= ep->num_ob_windows) + dev_err(pci->dev, "no free outbound window\n"); + + dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM, + pcie_ep->msi_phys_addr, + pcie_ep->msi_msg_addr, + PCIE_MSI_OB_SIZE); + + set_bit(free_win, &ep->ob_window_map); + ep->outbound_addr[free_win] = pcie_ep->msi_phys_addr; +} + +static int ls_pcie_raise_irq(struct dw_pcie_ep *ep, + enum pci_epc_irq_type type, u8 interrupt_num) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + struct ls_pcie *pcie = to_ls_pcie(pci); + struct ls_pcie_ep *pcie_ep = pcie->pcie_ep; + u32 index; + + ls_pcie_ep_msi_init(ep); + + ls_pcie_raise_msi_irq(pcie_ep); + + for (index = 0; index < ep->num_ob_windows; index++) { + if (ep->outbound_addr[index] == pcie_ep->msi_phys_addr) + break; + } + + if (index >= ep->num_ob_windows) + return -1; + + dw_pcie_disable_atu(pci, index, DW_PCIE_REGION_OUTBOUND); + clear_bit(index, &ep->ob_window_map); + + return 0; +} + +static struct dw_pcie_ep_ops pcie_ep_ops = { + .raise_irq = ls_pcie_raise_irq, +}; + +static int __init ls_add_pcie_ep(struct ls_pcie *pcie, + struct platform_device *pdev) +{ + struct dw_pcie *pci = pcie->pci; + struct device *dev = pci->dev; + struct dw_pcie_ep *ep; + struct ls_pcie_ep *pcie_ep; + struct resource *cfg_res; + int ret; + + ep = &pci->ep; + ep->ops = &pcie_ep_ops; + + pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL); + if (!pcie_ep) + return -ENOMEM; + + pcie->pcie_ep = pcie_ep; + + cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); + if (cfg_res) { + ep->phys_base = cfg_res->start; + ep->addr_size = PCIE_EP_ADDR_SPACE_SIZE; + } else { + dev_err(dev, "missing *config* space\n"); + return -ENODEV; + } + + ret = dw_pcie_ep_init(ep); + if (ret) { + dev_err(dev, "failed to initialize endpoint\n"); + return ret; + } + + return 0; + +} + static int __init ls_add_pcie_port(struct ls_pcie *pcie) { struct dw_pcie *pci = pcie->pci; @@ -309,16 +429,21 @@ static int __init ls_pcie_probe(struct platform_device *pdev) if (IS_ERR(pci->dbi_base)) return PTR_ERR(pci->dbi_base); - pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset; + pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_BASE; - if (!ls_pcie_is_bridge(pcie)) - return -ENODEV; + pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset; platform_set_drvdata(pdev, pcie); - ret = ls_add_pcie_port(pcie); - if (ret < 0) - return ret; + if (!ls_pcie_is_bridge(pcie)) { + ret = ls_add_pcie_ep(pcie, pdev); + if (ret < 0) + return ret; + } else { + ret = ls_add_pcie_port(pcie); + if (ret < 0) + return ret; + } return 0; }