From patchwork Thu Oct 26 14:28:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Shishkin X-Patchwork-Id: 10028445 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id F36AA6032C for ; Thu, 26 Oct 2017 14:33:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E4A5A28E36 for ; Thu, 26 Oct 2017 14:33:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D87CF28E3A; Thu, 26 Oct 2017 14:33:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4455928E36 for ; Thu, 26 Oct 2017 14:33:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932273AbdJZOdI (ORCPT ); Thu, 26 Oct 2017 10:33:08 -0400 Received: from mga09.intel.com ([134.134.136.24]:12064 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932234AbdJZOdH (ORCPT ); Thu, 26 Oct 2017 10:33:07 -0400 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Oct 2017 07:33:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.43,434,1503385200"; d="scan'208";a="1210418375" Received: from um.fi.intel.com (HELO localhost) ([10.237.72.212]) by fmsmga001.fm.intel.com with ESMTP; 26 Oct 2017 07:33:02 -0700 From: Alexander Shishkin To: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Shishkin , stable@vger.kernel.org Subject: [PATCH v1] PCI: Fixup the RTIT_BAR of Intel TH on Denverton Date: Thu, 26 Oct 2017 17:28:17 +0300 Message-Id: <20171026142817.17791-1-alexander.shishkin@linux.intel.com> X-Mailer: git-send-email 2.13.1 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On some integrations of the Intel(R) Trace Hub (for a reference and overview see Documentation/trace/intel_th.txt) the reported size of one of its resources (RTIT_BAR) doesn't match its actual size, which leads to overlaps with other devices' resources. On a Denverton platform it overlaps with XHCI MMIO space, which results in the xhci driver bailing out after seeing its registers as 0xffffffff, and perceived disappearance of all USB devices: > intel_th_pci 0000:00:1f.7: enabling device (0004 -> 0006) > xhci_hcd 0000:00:15.0: xHCI host controller not responding, assume dead > xhci_hcd 0000:00:15.0: xHC not responding in xhci_irq, assume controller is dead > xhci_hcd 0000:00:15.0: HC died; cleaning up > usb 1-1: USB disconnect, device number 2 ... For this reason, we need to resize the RTIT_BAR on Denverton to its actual size, which in this case is 4MB. Signed-off-by: Alexander Shishkin Link: https://software.intel.com/sites/default/files/managed/d3/3c/intel-th-developer-manual.pdf Fixes: 5118ccd34780 ("intel_th: pci: Add Denverton SOC support") Cc: stable@vger.kernel.org --- drivers/pci/quirks.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index a4d33619a7bb..d321ea6427b8 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4799,3 +4799,19 @@ static void quirk_no_ats(struct pci_dev *pdev) /* AMD Stoney platform GPU */ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats); #endif /* CONFIG_PCI_ATS */ + +static void quirk_intel_th_dnv(struct pci_dev *dev) +{ + struct resource *r = &dev->resource[4]; + + /* + * Denverton reports 2k of RTIT_BAR (intel_th resource 4), which + * appears to be 4 MB in reality. + */ + if (r->end == r->start + 0x7ff) { + r->start = 0; + r->end = 0x3fffff; + r->flags |= IORESOURCE_UNSET; + } +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x19e1, quirk_intel_th_dnv);