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[2/4] PCI: tegra: Reorder parameters in offset computations

Message ID 20171214134545.11143-3-thierry.reding@gmail.com (mailing list archive)
State New, archived
Delegated to: Bjorn Helgaas
Headers show

Commit Message

Thierry Reding Dec. 14, 2017, 1:45 p.m. UTC 
From: Thierry Reding <treding@nvidia.com>

The current computation of the configuration space offset is slightly
difficult to read because the fields aren't naturally ordered. This is
no doubt done to put extended register and register fields together,
but that's confusing because they are separate in the address mapping
given in the comment above the computations.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/pci/host/pci-tegra.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
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Patch

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 8a07c6f9e1b0..26b734c84850 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -372,11 +372,11 @@  static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset)
  * address (access to which generates correct config transaction) falls in
  * this 4 KiB region.
  */
-static unsigned long tegra_pcie_conf_offset(unsigned char b, unsigned int devfn,
-					    int where)
+static unsigned int tegra_pcie_conf_offset(u8 bus, unsigned int devfn,
+					   unsigned int where)
 {
-	return (b << 16) | (PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) |
-	       (((where & 0xf00) >> 8) << 24) | (where & 0xff);
+	return ((where & 0xf00) << 16) | (bus << 16) | (PCI_SLOT(devfn) << 11) |
+	       (PCI_FUNC(devfn) << 8) | (where & 0xff);
 }
 
 static int tegra_pcie_add_bus(struct pci_bus *bus)