From patchwork Mon Feb 12 18:33:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 10214061 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C9FA860153 for ; Mon, 12 Feb 2018 18:34:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C232028AB7 for ; Mon, 12 Feb 2018 18:34:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B664728CF6; Mon, 12 Feb 2018 18:34:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6554D28894 for ; Mon, 12 Feb 2018 18:34:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753741AbeBLSee (ORCPT ); Mon, 12 Feb 2018 13:34:34 -0500 Received: from foss.arm.com ([217.140.101.70]:46850 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754010AbeBLSec (ORCPT ); Mon, 12 Feb 2018 13:34:32 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C1CDC165C; Mon, 12 Feb 2018 10:34:31 -0800 (PST) Received: from e106794-lin.cambridge.arm.com (e106794-lin.cambridge.arm.com [10.1.210.24]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E4DE43F24D; Mon, 12 Feb 2018 10:34:25 -0800 (PST) From: Jean-Philippe Brucker To: linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux-foundation.org, kvm@vger.kernel.org Cc: joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, lorenzo.pieralisi@arm.com, hanjun.guo@linaro.org, sudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org, robin.murphy@arm.com, bhelgaas@google.com, alex.williamson@redhat.com, tn@semihalf.com, liubo95@huawei.com, thunder.leizhen@huawei.com, xieyisheng1@huawei.com, xuzaibo@huawei.com, ilias.apalodimas@linaro.org, jonathan.cameron@huawei.com, shunyong.yang@hxt-semitech.com, nwatters@codeaurora.org, okaya@codeaurora.org, jcrouse@codeaurora.org, rfranz@cavium.com, dwmw2@infradead.org, jacob.jun.pan@linux.intel.com, yi.l.liu@intel.com, ashok.raj@intel.com, robdclark@gmail.com, christian.koenig@amd.com, bharatku@xilinx.com Subject: [PATCH 36/37] iommu/arm-smmu-v3: Add support for PCI PASID Date: Mon, 12 Feb 2018 18:33:51 +0000 Message-Id: <20180212183352.22730-37-jean-philippe.brucker@arm.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180212183352.22730-1-jean-philippe.brucker@arm.com> References: <20180212183352.22730-1-jean-philippe.brucker@arm.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Enable PASID for PCI devices that support it. Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm-smmu-v3.c | 54 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index ace2f995b0c0..26935a9a5a97 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -2608,6 +2608,52 @@ static void arm_smmu_disable_pri(struct arm_smmu_master_data *master) master->can_fault = false; } +static int arm_smmu_enable_pasid(struct arm_smmu_master_data *master) +{ + int ret; + int features; + u8 pasid_bits; + int num_pasids; + struct pci_dev *pdev; + + if (!dev_is_pci(master->dev)) + return -ENOSYS; + + pdev = to_pci_dev(master->dev); + + features = pci_pasid_features(pdev); + if (features < 0) + return -ENOSYS; + + num_pasids = pci_max_pasids(pdev); + if (num_pasids <= 0) + return -ENOSYS; + + pasid_bits = min_t(u8, ilog2(num_pasids), master->smmu->ssid_bits); + + dev_dbg(&pdev->dev, "device supports %#x PASID bits [%s%s]\n", pasid_bits, + (features & PCI_PASID_CAP_EXEC) ? "x" : "", + (features & PCI_PASID_CAP_PRIV) ? "p" : ""); + + ret = pci_enable_pasid(pdev, features); + return ret ? ret : pasid_bits; +} + +static void arm_smmu_disable_pasid(struct arm_smmu_master_data *master) +{ + struct pci_dev *pdev; + + if (!dev_is_pci(master->dev)) + return; + + pdev = to_pci_dev(master->dev); + + if (!pdev->pasid_enabled) + return; + + pci_disable_pasid(pdev); +} + static int arm_smmu_insert_master(struct arm_smmu_device *smmu, struct arm_smmu_master_data *master) { @@ -2728,6 +2774,11 @@ static int arm_smmu_add_device(struct device *dev) master->ste.can_stall = true; } + /* PASID must be enabled before ATS */ + ret = arm_smmu_enable_pasid(master); + if (ret > 0) + master->ssid_bits = ret; + if (!arm_smmu_enable_ats(master)) arm_smmu_enable_pri(master); @@ -2746,6 +2797,7 @@ static int arm_smmu_add_device(struct device *dev) err_disable_pri: arm_smmu_disable_pri(master); arm_smmu_disable_ats(master); + arm_smmu_disable_pasid(master); return ret; } @@ -2766,7 +2818,9 @@ static void arm_smmu_remove_device(struct device *dev) arm_smmu_remove_master(smmu, master); arm_smmu_disable_pri(master); + /* PASID must be disabled after ATS */ arm_smmu_disable_ats(master); + arm_smmu_disable_pasid(master); iommu_group_remove_device(dev); iommu_device_unlink(&smmu->iommu, dev);