From patchwork Tue May 22 22:28:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajat Jain X-Patchwork-Id: 10419695 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 33C616032A for ; Tue, 22 May 2018 22:29:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1C40F28C6C for ; Tue, 22 May 2018 22:29:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 100A828F26; Tue, 22 May 2018 22:29:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI, USER_IN_DEF_DKIM_WL autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 75C6B28C6C for ; Tue, 22 May 2018 22:29:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753306AbeEVW2W (ORCPT ); Tue, 22 May 2018 18:28:22 -0400 Received: from mail-pl0-f66.google.com ([209.85.160.66]:40066 "EHLO mail-pl0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753292AbeEVW2S (ORCPT ); Tue, 22 May 2018 18:28:18 -0400 Received: by mail-pl0-f66.google.com with SMTP id t12-v6so11728750plo.7 for ; Tue, 22 May 2018 15:28:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mtQg0C2UxAO/yt2e3Y4t/QmkuaI+TKeGb8xRnoTLuus=; b=XzKghhGT8kEaFjl0XnEgx5xVRyvUmS/6CEUb6eT7OUJweFHiLJtFqwCekVC5b1QqDv IB04QJ7LbKmtE6guxC6OAahSqMobG3LtAZQo8v+doB+NgHk56OPP5pQCg7Zwh4WXEP1C W3PpccVSIBJj3xzJLY2fXiEU/7ep1zxs25eesi5k//4KrAmomHnwpAAzMv60UOkGsl+r rhv+IHFgUagJCfAdfpGR/sI51VEO+oHTdFiCK5uE4c1Fs5sTXgH8gqRthFVa4IUXf0hg lIyP6eaYFJs877bNh2kXrUvwiT+s8KrOhkw3cKpIr4av7AmdFbkKYpMywksl3kZ9x8mE 5q6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mtQg0C2UxAO/yt2e3Y4t/QmkuaI+TKeGb8xRnoTLuus=; b=biai9kBSbTWtu96fDoNbVaPk2F/ypBJklD4vOl/iAUMAps8F+GthbCupZEEAaL5oAN fjYzf4ebxr7GMaWsREGrBAANeOLI2qsu/3vZ88hlP+2KESwG/phWl5JULlVsHLaI1/Qo qgMseSk5xksg+iGGDwb1NW0HKHKDgvffYfgqk3KmyriqA6/2IXL/FOIGfPl2atZQYvUm YRSQG70NiqRRhzwm3ecj2q56wqchHCOa0U1XkK/+AFWbqpMO+m8g3MljjEvv8xc+cAXF E8FD6UNfa+yj3F+Hbvg0xHO5jbfHs6Zb774FPQAwf0EyMfZVjjFsdD+Qo8ZBl00KtJow axnA== X-Gm-Message-State: ALKqPwf5HYRudN2WZ/GjlDxh9lTApzQD7lEB6BsncyF7uGXHnU2mi7hx QdBnSzwFRGXXAV9SCOc84qBztg== X-Google-Smtp-Source: AB8JxZpNhw4VXbT2CxbzrT9u6L5T4hwTxZX+LOVEuErVrhrBIODbod1uV0evQ0rFZUZDf1sD9JT5kw== X-Received: by 2002:a17:902:2927:: with SMTP id g36-v6mr287978plb.303.1527028097634; Tue, 22 May 2018 15:28:17 -0700 (PDT) Received: from rajat.mtv.corp.google.com ([2620:0:1000:1501:dc81:9a9e:fdee:decf]) by smtp.gmail.com with ESMTPSA id b72-v6sm34327852pfm.69.2018.05.22.15.28.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 22 May 2018 15:28:17 -0700 (PDT) From: Rajat Jain To: Bjorn Helgaas , Jonathan Corbet , Philippe Ombredanne , Kate Stewart , Thomas Gleixner , Greg Kroah-Hartman , Rajat Jain , Frederick Lawler , Oza Pawandeep , Keith Busch , Gabriele Paoloni , Alexandru Gagniuc , Thomas Tai , "Steven Rostedt (VMware)" , linux-pci@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Jes Sorensen , Kyle McMartin Cc: rajatxjain@gmail.com Subject: [PATCH 1/5] PCI/AER: Define and allocate aer_stats structure for AER capable devices Date: Tue, 22 May 2018 15:28:01 -0700 Message-Id: <20180522222805.80314-2-rajatja@google.com> X-Mailer: git-send-email 2.17.0.441.gb46fe60e1d-goog In-Reply-To: <20180522222805.80314-1-rajatja@google.com> References: <20180522222805.80314-1-rajatja@google.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Define a structure to hold the AER statistics. There are 2 groups of statistics: dev_* counters that are to be collected for all AER capable devices and rootport_* counters that are collected for all (AER capable) rootports only. Allocate and free this structure when device is added or released (thus counters survive the lifetime of the device). Add a new file aerdrv_stats.c to hold the AER stats collection logic. Signed-off-by: Rajat Jain --- drivers/pci/pcie/aer/Makefile | 2 +- drivers/pci/pcie/aer/aerdrv.h | 6 +++ drivers/pci/pcie/aer/aerdrv_core.c | 9 ++++ drivers/pci/pcie/aer/aerdrv_stats.c | 64 +++++++++++++++++++++++++++++ drivers/pci/probe.c | 1 + include/linux/pci.h | 3 ++ 6 files changed, 84 insertions(+), 1 deletion(-) create mode 100644 drivers/pci/pcie/aer/aerdrv_stats.c diff --git a/drivers/pci/pcie/aer/Makefile b/drivers/pci/pcie/aer/Makefile index 09bd890875a3..a06f9cc2bde5 100644 --- a/drivers/pci/pcie/aer/Makefile +++ b/drivers/pci/pcie/aer/Makefile @@ -7,7 +7,7 @@ obj-$(CONFIG_PCIEAER) += aerdriver.o obj-$(CONFIG_PCIE_ECRC) += ecrc.o -aerdriver-objs := aerdrv_errprint.o aerdrv_core.o aerdrv.o +aerdriver-objs := aerdrv_errprint.o aerdrv_core.o aerdrv.o aerdrv_stats.o aerdriver-$(CONFIG_ACPI) += aerdrv_acpi.o obj-$(CONFIG_PCIEAER_INJECT) += aer_inject.o diff --git a/drivers/pci/pcie/aer/aerdrv.h b/drivers/pci/pcie/aer/aerdrv.h index b4c950683cc7..d8b9fba536ed 100644 --- a/drivers/pci/pcie/aer/aerdrv.h +++ b/drivers/pci/pcie/aer/aerdrv.h @@ -33,6 +33,10 @@ PCI_ERR_UNC_MALF_TLP) #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ + +#define AER_MAX_TYPEOF_CORRECTABLE_ERRS 16 /* as per PCI_ERR_COR_STATUS */ +#define AER_MAX_TYPEOF_UNCORRECTABLE_ERRS 26 /* as per PCI_ERR_UNCOR_STATUS*/ + struct aer_err_info { struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; int error_dev_num; @@ -81,6 +85,8 @@ void aer_isr(struct work_struct *work); void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info); irqreturn_t aer_irq(int irq, void *context); +int pci_aer_stats_init(struct pci_dev *pdev); +void pci_aer_stats_exit(struct pci_dev *pdev); #ifdef CONFIG_ACPI_APEI int pcie_aer_get_firmware_first(struct pci_dev *pci_dev); diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c index 36e622d35c48..42a6f913069a 100644 --- a/drivers/pci/pcie/aer/aerdrv_core.c +++ b/drivers/pci/pcie/aer/aerdrv_core.c @@ -95,9 +95,18 @@ int pci_cleanup_aer_error_status_regs(struct pci_dev *dev) int pci_aer_init(struct pci_dev *dev) { dev->aer_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); + + if (!dev->aer_cap || pci_aer_stats_init(dev)) + return -EIO; + return pci_cleanup_aer_error_status_regs(dev); } +void pci_aer_exit(struct pci_dev *dev) +{ + pci_aer_stats_exit(dev); +} + /** * add_error_device - list device to be handled * @e_info: pointer to error info diff --git a/drivers/pci/pcie/aer/aerdrv_stats.c b/drivers/pci/pcie/aer/aerdrv_stats.c new file mode 100644 index 000000000000..b9f251992209 --- /dev/null +++ b/drivers/pci/pcie/aer/aerdrv_stats.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Google Inc, All Rights Reserved. + * Rajat Jain (rajatja@google.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * AER Statistics - exposed to userspace via /sysfs attributes. + */ + +#include +#include "aerdrv.h" + +/* AER stats for the device */ +struct aer_stats { + + /* + * Fields for all AER capable devices. They indicate the errors + * "as seen by this device". Note that this may mean that if an + * end point is causing problems, the AER counters may increment + * at its link partner (e.g. root port) because the errors will be + * "seen" by the link partner and not the the problematic end point + * itself (which may report all counters as 0 as it never saw any + * problems). + */ + /* Individual counters for different type of correctable errors */ + u64 dev_cor_errs[AER_MAX_TYPEOF_CORRECTABLE_ERRS]; + /* Individual counters for different type of uncorrectable errors */ + u64 dev_uncor_errs[AER_MAX_TYPEOF_UNCORRECTABLE_ERRS]; + /* Total number of correctable errors seen by this device */ + u64 dev_total_cor_errs; + /* Total number of fatal uncorrectable errors seen by this device */ + u64 dev_total_fatal_errs; + /* Total number of fatal uncorrectable errors seen by this device */ + u64 dev_total_nonfatal_errs; + + /* + * Fields for Root ports only, these indicate the total number of + * ERR_COR, ERR_FATAL, and ERR_NONFATAL messages received by the + * rootport, INCLUDING the ones that are generated internally (by + * the rootport itself) + */ + u64 rootport_total_cor_errs; + u64 rootport_total_fatal_errs; + u64 rootport_total_nonfatal_errs; +}; + +int pci_aer_stats_init(struct pci_dev *pdev) +{ + pdev->aer_stats = kzalloc(sizeof(struct aer_stats), GFP_KERNEL); + if (!pdev->aer_stats) { + dev_err(&pdev->dev, "No memory for aer_stats\n"); + return -ENOMEM; + } + return 0; +} + +void pci_aer_stats_exit(struct pci_dev *pdev) +{ + kfree(pdev->aer_stats); + pdev->aer_stats = NULL; +} diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 384020757b81..dd662c241373 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2064,6 +2064,7 @@ static void pci_configure_device(struct pci_dev *dev) static void pci_release_capabilities(struct pci_dev *dev) { + pci_aer_exit(dev); pci_vpd_release(dev); pci_iov_release(dev); pci_free_cap_save_buffers(dev); diff --git a/include/linux/pci.h b/include/linux/pci.h index 21965e0dbe62..5c84b1304de7 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -299,6 +299,7 @@ struct pci_dev { u8 hdr_type; /* PCI header type (`multi' flag masked out) */ #ifdef CONFIG_PCIEAER u16 aer_cap; /* AER capability offset */ + struct aer_stats *aer_stats; /* AER stats for this device */ #endif u8 pcie_cap; /* PCIe capability offset */ u8 msi_cap; /* MSI capability offset */ @@ -1470,10 +1471,12 @@ static inline bool pcie_aspm_support_enabled(void) { return false; } void pci_no_aer(void); bool pci_aer_available(void); int pci_aer_init(struct pci_dev *dev); +void pci_aer_exit(struct pci_dev *dev); #else static inline void pci_no_aer(void) { } static inline bool pci_aer_available(void) { return false; } static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; } +static inline void pci_aer_exit(struct pci_dev *d) { } #endif #ifdef CONFIG_PCIE_ECRC