From patchwork Wed Aug 1 15:14:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 10552445 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 15FFC15E9 for ; Wed, 1 Aug 2018 15:14:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 076C62B6FC for ; Wed, 1 Aug 2018 15:14:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EF5952B738; Wed, 1 Aug 2018 15:14:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 98DCD2B6FC for ; Wed, 1 Aug 2018 15:14:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389683AbeHARA0 (ORCPT ); Wed, 1 Aug 2018 13:00:26 -0400 Received: from bombadil.infradead.org ([198.137.202.133]:50238 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389611AbeHARAZ (ORCPT ); Wed, 1 Aug 2018 13:00:25 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=References:In-Reply-To:Message-Id: Date:Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=o/ehVBmEX6ouGSgXHAnvlHZTFRH3dNb6FPW+Uhrzvxc=; b=cpjAulqolYNTWjBZ3Os8kA/66 czc58HZ5/Z9SPviCCKxz1QvZnKjLf8TMvEAWYRxcyQtAAf4gYB6nvEHsynhUQWkB93N99nsEAGuv+ fc/4epuuxicH7xxXdlMfNf3P3eZgGnoB7x6PhEkzcdoUun3OHRQUtltSFUZBvDngs9rpqayhSBFI2 gZ48p4cWSOlNbH63LOQvLz4Y1UDfWuO5Pd52pIg+cWNKdjEd6ENR3SNkVv7dh9PJF0C/rQfbZc8kh LWyPwOWsjic67fM/kcVoXNW680w/ZgXv0THIg7vASpY6AXNIBI99KaelQDB5Zga5u3YQY+98uzuHh 6xQVlh2bQ==; Received: from clnet-p19-102.ikbnet.co.at ([83.175.77.102] helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.90_1 #2 (Red Hat Linux)) id 1fkspH-0004ul-Ul; Wed, 01 Aug 2018 15:14:12 +0000 From: Christoph Hellwig To: Lorenzo Pieralisi , Bjorn Helgaas Cc: Palmer Dabbelt , "Wesley W . Terpstra" , Arnd Bergmann , linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 2/3] PCI/xilinx: Work-around for hardware DMA limit (32 bits) Date: Wed, 1 Aug 2018 17:14:02 +0200 Message-Id: <20180801151403.20660-3-hch@lst.de> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180801151403.20660-1-hch@lst.de> References: <20180801151403.20660-1-hch@lst.de> X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This PCIe bridge only has a 32 bit bus master interface, thus truncating the DMA capability of all PCIe devices attached beneath it. This caps the child device capability so that these devices work on systems with physical memory beyond the 4GiB threshold. Based on an earlier patch from Wesley W. Terpstra . Signed-off-by: Christoph Hellwig --- drivers/pci/controller/pcie-xilinx.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pci/controller/pcie-xilinx.c b/drivers/pci/controller/pcie-xilinx.c index 7b1389d8e2a5..da65b18aa45e 100644 --- a/drivers/pci/controller/pcie-xilinx.c +++ b/drivers/pci/controller/pcie-xilinx.c @@ -197,6 +197,15 @@ static void __iomem *xilinx_pcie_map_bus(struct pci_bus *bus, return port->reg_base + relbus + where; } +/* + * This PCIe bridge only has a 32 bit bus master interface, thus truncating + * the DMA capability of all PCIe devices attached beneath it. + */ +static void xilinx_pcie_add_dev(struct pci_dev *pdev) +{ + pdev->dev.bus_dma_mask = DMA_BIT_MASK(32); +} + /* PCIe operations */ static struct pci_ops xilinx_pcie_ops = { .map_bus = xilinx_pcie_map_bus, @@ -665,6 +674,7 @@ static int xilinx_pcie_probe(struct platform_device *pdev) bridge->ops = &xilinx_pcie_ops; bridge->map_irq = of_irq_parse_and_map_pci; bridge->swizzle_irq = pci_common_swizzle; + bridge->add_dev = xilinx_pcie_add_dev; #ifdef CONFIG_PCI_MSI xilinx_pcie_msi_chip.dev = dev;