From patchwork Mon May 13 18:07:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 10941477 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 45B9D76 for ; Mon, 13 May 2019 18:08:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 38E7D283A8 for ; Mon, 13 May 2019 18:08:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2D420283C9; Mon, 13 May 2019 18:08:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CA5C1283A8 for ; Mon, 13 May 2019 18:08:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732266AbfEMSIj (ORCPT ); Mon, 13 May 2019 14:08:39 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:3160 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732237AbfEMSIi (ORCPT ); Mon, 13 May 2019 14:08:38 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 13 May 2019 11:07:58 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 13 May 2019 11:08:38 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 13 May 2019 11:08:38 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 13 May 2019 18:08:37 +0000 Received: from manikanta-bm2.nvidia.com (172.20.13.39) by HQMAIL.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Mon, 13 May 2019 18:08:34 +0000 From: Manikanta Maddireddy To: , , , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V3 09/29] PCI: tegra: Enable opportunistic UpdateFC and ACK Date: Mon, 13 May 2019 23:37:24 +0530 Message-ID: <20190513180744.16493-10-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190513180744.16493-1-mmaddireddy@nvidia.com> References: <20190513180744.16493-1-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1557770878; bh=E0raxA3vS1MrP1SZ2FtMqcjU7EKidQSlPDvqUbdZGx4=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=HJTQL/MwT9zDIr5HSIET7RVZ3DRDWam3AQvpD6jID2t60JOONoKJF9W+c3PUIdbhk eTeTd4eMN2xt8YM7gBnscQwgC9l0j1BVAn9/UwsRQWVO7ofdGc1IrBLQSrGJR9lyIq M/Z4mGsBl/jOhbqNvsXDQx0ED+HY/IEXmgPqNItJkIyFDWWXXqElLWoEko/LGgMZpn +JWCw96f/H95zVJhXGYCPphWiHVmV45In5wM5hCkZGGh6rW0HM0ZOIMY+8Hzcfnyv3 p0p0EqBi8NKiMQ6qtJKnAARtC/jchvx3xKcZNvBTralKGALHVKQ+3m2swcFamvddbw jXO2oFu5fGGog== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Enable opportunistic UpdateFC and ACK to allow data link layer send pending ACKs and UpdateFC packets when link is idle instead of waiting for timers to expire. This improves the PCIe performance due to better utilization of PCIe bandwidth. Signed-off-by: Manikanta Maddireddy Acked-by: Thierry Reding --- V3: No change V2: No change drivers/pci/controller/pci-tegra.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index 76d913ef5bf4..b1e2e398b4e8 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -204,7 +204,9 @@ #define RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK 0xffffffff #define RP_VEND_XP 0x00000f00 -#define RP_VEND_XP_DL_UP (1 << 30) +#define RP_VEND_XP_DL_UP (1 << 30) +#define RP_VEND_XP_OPPORTUNISTIC_ACK (1 << 27) +#define RP_VEND_XP_OPPORTUNISTIC_UPDATEFC (1 << 28) #define RP_VEND_CTL1 0x00000f48 #define RP_VEND_CTL1_ERPT (1 << 13) @@ -529,6 +531,12 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port) value = readl(port->base + RP_VEND_CTL1); value |= RP_VEND_CTL1_ERPT; writel(value, port->base + RP_VEND_CTL1); + + /* Optimal settings to enhance bandwidth */ + value = readl(port->base + RP_VEND_XP); + value |= RP_VEND_XP_OPPORTUNISTIC_ACK; + value |= RP_VEND_XP_OPPORTUNISTIC_UPDATEFC; + writel(value, port->base + RP_VEND_XP); } static void tegra_pcie_program_ectl_settings(struct tegra_pcie_port *port)