From patchwork Mon May 13 18:07:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 10941463 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8310576 for ; Mon, 13 May 2019 18:08:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 75AE3283A8 for ; Mon, 13 May 2019 18:08:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6A0CB283C9; Mon, 13 May 2019 18:08:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0EDE3283A8 for ; Mon, 13 May 2019 18:08:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732262AbfEMSIJ (ORCPT ); Mon, 13 May 2019 14:08:09 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:18024 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731142AbfEMSIJ (ORCPT ); Mon, 13 May 2019 14:08:09 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 13 May 2019 11:08:15 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 13 May 2019 11:08:08 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 13 May 2019 11:08:08 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 13 May 2019 18:08:08 +0000 Received: from manikanta-bm2.nvidia.com (172.20.13.39) by HQMAIL.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Mon, 13 May 2019 18:08:03 +0000 From: Manikanta Maddireddy To: , , , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V3 02/29] PCI: tegra: Handle failure cases in tegra_pcie_power_on() Date: Mon, 13 May 2019 23:37:17 +0530 Message-ID: <20190513180744.16493-3-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190513180744.16493-1-mmaddireddy@nvidia.com> References: <20190513180744.16493-1-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1557770895; bh=D+9rVvsvnkjYePhtWdQRd2ybIXzuQ0q3aqrtG2YHq0o=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=rcGZXcIl2dhVU+Er8d44BRtTmUvZK/rsQOBdJANm17r0mafJYpBG52kBafX0vY2jn rY7ReweXJGWqx8WjStY3iZgfEnozWYaMPnXLv8c3yCJbKdag6Z/qU+rbn5rMEFpi9M 8PWtJr0Hh5JD4CZXfyhJJRxbK67UtOLHFOSK/wHbmR1ue+79U+hfj+EnOzXCw2QxCT 39EEYXxV3VDMbBWPCm48klIWFYDLjthDp2zqM9baS+e55R308ZOBc3XUmGUKozQqh7 rYhbqIV7aSbUsPFJ031656Xk9UsIYwMfU6A9DGzBQ/Ue5bIfUMO/G5KyWtMd1E/JQO Yko0qbsWGn+pA== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Unroll the PCIe power on sequence if any one of the steps fail in tegra_pcie_power_on(). Signed-off-by: Manikanta Maddireddy Acked-by: Thierry Reding --- V3: No change V2: New patch to handle error cleanup in tegra_pcie_power_on(). drivers/pci/controller/pci-tegra.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index f4f53d092e00..8235d937951b 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -1052,7 +1052,7 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie) err = clk_prepare_enable(pcie->pex_clk); if (err) { dev_err(dev, "failed to enable PEX clock: %d\n", err); - return err; + goto regulator_disable; } reset_control_deassert(pcie->pex_rst); } else { @@ -1061,7 +1061,7 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie) pcie->pex_rst); if (err) { dev_err(dev, "powerup sequence failed: %d\n", err); - return err; + goto regulator_disable; } } @@ -1070,24 +1070,40 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie) err = clk_prepare_enable(pcie->afi_clk); if (err < 0) { dev_err(dev, "failed to enable AFI clock: %d\n", err); - return err; + goto powergate; } if (soc->has_cml_clk) { err = clk_prepare_enable(pcie->cml_clk); if (err < 0) { dev_err(dev, "failed to enable CML clock: %d\n", err); - return err; + goto disable_afi_clk; } } err = clk_prepare_enable(pcie->pll_e); if (err < 0) { dev_err(dev, "failed to enable PLLE clock: %d\n", err); - return err; + goto disable_cml_clk; } return 0; + +disable_cml_clk: + if (soc->has_cml_clk) + clk_disable_unprepare(pcie->cml_clk); +disable_afi_clk: + clk_disable_unprepare(pcie->afi_clk); +powergate: + reset_control_assert(pcie->afi_rst); + reset_control_assert(pcie->pex_rst); + clk_disable_unprepare(pcie->pex_clk); + if (!dev->pm_domain) + tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); +regulator_disable: + regulator_bulk_disable(pcie->num_supplies, pcie->supplies); + + return err; } static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)