From patchwork Mon May 13 18:07:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 10941473 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EEE54933 for ; Mon, 13 May 2019 18:08:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E2D57283A8 for ; Mon, 13 May 2019 18:08:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D76B1283C9; Mon, 13 May 2019 18:08:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 83D49283A8 for ; Mon, 13 May 2019 18:08:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732288AbfEMSIb (ORCPT ); Mon, 13 May 2019 14:08:31 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:3140 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731484AbfEMSIb (ORCPT ); Mon, 13 May 2019 14:08:31 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 13 May 2019 11:07:51 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 13 May 2019 11:08:31 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 13 May 2019 11:08:31 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 13 May 2019 18:08:30 +0000 Received: from manikanta-bm2.nvidia.com (172.20.13.39) by HQMAIL.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Mon, 13 May 2019 18:08:27 +0000 From: Manikanta Maddireddy To: , , , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V3 07/29] PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability Date: Mon, 13 May 2019 23:37:22 +0530 Message-ID: <20190513180744.16493-8-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190513180744.16493-1-mmaddireddy@nvidia.com> References: <20190513180744.16493-1-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1557770871; bh=+TtWqZqrE7VeJZIzB5ce4CWxiF6hCQiaxiV2Rbvj2Ys=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=NsautjP0kmP0OZxdtHc2fKj5INS95OcZUWtrwG4dKuH1rmp1aXCx2wfA84e6v4V1x aEZJ7M+i8Y7NsWkjew3SVlC37NKSHEqpYYYgWn185qHUExthB+y/ag4y0mBd1sG1Sr xfmZvrZTabGzx6NKsn1JQ3pzgIVrV00AUd61dmh2NrbS2EgxQHwR5t4fhW5Wi7Gc2B QWHKP+iHCT58ULq1QugrTRUSNr9GeAskVmisxVm+whu7KiCMU+6optJRPvbsaAGE+C FG9VP3LkFC2sV8+WtTZXSKS7bSEwcw7q30GgWHWLoL6Jc8rvHrPSvvDtlqtKGEUF54 6l6FsMR/kcz3w== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Default root port setting hides AER capability. This patch enables the advertisement of AER capability by root port. Signed-off-by: Manikanta Maddireddy Acked-by: Thierry Reding --- V3: No change V2: No change drivers/pci/controller/pci-tegra.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index cd542a8af618..e402627bd221 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -180,6 +180,9 @@ #define RP_VEND_XP 0x00000f00 #define RP_VEND_XP_DL_UP (1 << 30) +#define RP_VEND_CTL1 0x00000f48 +#define RP_VEND_CTL1_ERPT (1 << 13) + #define RP_VEND_CTL2 0x00000fa8 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7) @@ -479,6 +482,16 @@ static void tegra_pcie_port_reset(struct tegra_pcie_port *port) afi_writel(port->pcie, value, ctrl); } +static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port) +{ + u32 value; + + /* Enable AER capability */ + value = readl(port->base + RP_VEND_CTL1); + value |= RP_VEND_CTL1_ERPT; + writel(value, port->base + RP_VEND_CTL1); +} + static void tegra_pcie_port_enable(struct tegra_pcie_port *port) { unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); @@ -503,6 +516,8 @@ static void tegra_pcie_port_enable(struct tegra_pcie_port *port) value |= RP_VEND_CTL2_PCA_ENABLE; writel(value, port->base + RP_VEND_CTL2); } + + tegra_pcie_enable_rp_features(port); } static void tegra_pcie_port_disable(struct tegra_pcie_port *port)