diff mbox series

[V5,25/27] PCI: Add DT binding for "reset-gpios" property

Message ID	20190617173952.29363-26-mmaddireddy@nvidia.com (mailing list archive)
State	Superseded, archived
Headers	show Return-Path: <linux-pci-owner@kernel.org> TLS: TLSv1.2, DES-CBC3-SHA) id <B5d07d0c30003>; Mon, 17 Jun 2019 10:41:23 -0700 From: Manikanta Maddireddy <mmaddireddy@nvidia.com> To: <thierry.reding@gmail.com>, <bhelgaas@google.com>, <robh+dt@kernel.org>, <mark.rutland@arm.com>, <jonathanh@nvidia.com>, <lorenzo.pieralisi@arm.com>, <vidyas@nvidia.com> CC: <linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>, Manikanta Maddireddy <mmaddireddy@nvidia.com> Subject: [PATCH V5 25/27] PCI: Add DT binding for "reset-gpios" property Date: Mon, 17 Jun 2019 23:09:50 +0530 Message-ID: <20190617173952.29363-26-mmaddireddy@nvidia.com> In-Reply-To: <20190617173952.29363-1-mmaddireddy@nvidia.com> References: <20190617173952.29363-1-mmaddireddy@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-pci-owner@vger.kernel.org Precedence: bulk
Series	Enable Tegra PCIe root port features \| expand [V5,00/27] Enable Tegra PCIe root port features [V5,01/27] soc/tegra: pmc: Export tegra_powergate_power_on() [V5,02/27] PCI: tegra: Handle failure cases in tegra_pcie_power_on() [V5,03/27] PCI: tegra: Rearrange Tegra PCIe driver functions [V5,04/27] PCI: tegra: Mask AFI_INTR in runtime suspend [V5,05/27] PCI: tegra: Fix PCIe host power up sequence [V5,06/27] PCI: tegra: Add PCIe Gen2 link speed support [V5,07/27] PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability [V5,08/27] PCI: tegra: Program UPHY electrical settings for Tegra210 [V5,09/27] PCI: tegra: Enable opportunistic UpdateFC and ACK [V5,10/27] PCI: tegra: Disable AFI dynamic clock gating [V5,11/27] PCI: tegra: Process pending DLL transactions before entering L1 or L2 [V5,12/27] PCI: tegra: Enable PCIe xclk clock clamping [V5,13/27] PCI: tegra: Increase the deskew retry time [V5,14/27] PCI: tegra: Add SW fixup for RAW violations [V5,15/27] PCI: tegra: Update flow control timer frequency in Tegra210 [V5,16/27] PCI: tegra: Set target speed as Gen1 before starting LTSSM [V5,17/27] PCI: tegra: Fix PLLE power down issue due to CLKREQ# signal [V5,18/27] PCI: tegra: Program AFI_CACHE* registers only for Tegra20 [V5,19/27] PCI: tegra: Change PRSNT_SENSE IRQ log to debug [V5,20/27] PCI: tegra: Use legacy IRQ for port service drivers [V5,21/27] PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of soc struct [V5,22/27] dt-bindings: pci: tegra: Document PCIe DPD pinctrl optional prop [V5,23/27] arm64: tegra: Add PEX DPD states as pinctrl properties [V5,24/27] PCI: tegra: Put PEX CLK & BIAS pads in DPD mode [V5,25/27] PCI: Add DT binding for "reset-gpios" property [V5,26/27] PCI: tegra: Add support for GPIO based PERST# [V5,27/27] PCI: tegra: Change link retry log level to debug

Commit Message

Manikanta Maddireddy June 17, 2019, 5:39 p.m. UTC

Add DT binding for "reset-gpios" property which supports GPIO based PERST#
signal.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Thierry Reding <treding@nvidia.com>
---
V5: No change

V4: No change

V3: Moved to common pci binding doc

V2: Using standard "reset-gpio" property

 Documentation/devicetree/bindings/pci/pci.txt | 3 +++
 1 file changed, 3 insertions(+)

diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt
index c77981c5dd18..79124898aa5b 100644
--- a/Documentation/devicetree/bindings/pci/pci.txt
+++ b/Documentation/devicetree/bindings/pci/pci.txt
@@ -24,3 +24,6 @@  driver implementation may support the following properties:
    unsupported link speed, for instance, trying to do training for
    unsupported link speed, etc.  Must be '4' for gen4, '3' for gen3, '2'
    for gen2, and '1' for gen1. Any other values are invalid.
+- reset-gpios:
+   If present this property specifies PERST# GPIO. Host drivers can parse the
+   GPIO and apply fundamental reset to endpoints.