diff mbox series

[V6,27/27] PCI: tegra: Change link retry log level to debug

Message ID	20190618180206.4908-28-mmaddireddy@nvidia.com (mailing list archive)
State	New, archived
Delegated to:	Bjorn Helgaas
Headers	show Return-Path: <linux-pci-owner@kernel.org> TLS: TLSv1.2, DES-CBC3-SHA) id <B5d0927820000>; Tue, 18 Jun 2019 11:03:46 -0700 From: Manikanta Maddireddy <mmaddireddy@nvidia.com> To: <thierry.reding@gmail.com>, <bhelgaas@google.com>, <robh+dt@kernel.org>, <mark.rutland@arm.com>, <jonathanh@nvidia.com>, <lorenzo.pieralisi@arm.com>, <vidyas@nvidia.com> CC: <linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>, Manikanta Maddireddy <mmaddireddy@nvidia.com> Subject: [PATCH V6 27/27] PCI: tegra: Change link retry log level to debug Date: Tue, 18 Jun 2019 23:32:06 +0530 Message-ID: <20190618180206.4908-28-mmaddireddy@nvidia.com> In-Reply-To: <20190618180206.4908-1-mmaddireddy@nvidia.com> References: <20190618180206.4908-1-mmaddireddy@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-pci-owner@vger.kernel.org Precedence: bulk
Series	Enable Tegra PCIe root port features \| expand [V6,00/27] Enable Tegra PCIe root port features [V6,01/27] soc/tegra: pmc: Export tegra_powergate_power_on() [V6,02/27] PCI: tegra: Handle failure cases in tegra_pcie_power_on() [V6,03/27] PCI: tegra: Rearrange Tegra PCIe driver functions [V6,04/27] PCI: tegra: Mask AFI_INTR in runtime suspend [V6,05/27] PCI: tegra: Fix PCIe host power up sequence [V6,06/27] PCI: tegra: Add PCIe Gen2 link speed support [V6,07/27] PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability [V6,08/27] PCI: tegra: Program UPHY electrical settings for Tegra210 [V6,09/27] PCI: tegra: Enable opportunistic UpdateFC and ACK [V6,10/27] PCI: tegra: Disable AFI dynamic clock gating [V6,11/27] PCI: tegra: Process pending DLL transactions before entering L1 or L2 [V6,12/27] PCI: tegra: Enable PCIe xclk clock clamping [V6,13/27] PCI: tegra: Increase the deskew retry time [V6,14/27] PCI: tegra: Add SW fixup for RAW violations [V6,15/27] PCI: tegra: Update flow control timer frequency in Tegra210 [V6,16/27] PCI: tegra: Set target speed as Gen1 before starting LTSSM [V6,17/27] PCI: tegra: Fix PLLE power down issue due to CLKREQ# signal [V6,18/27] PCI: tegra: Program AFI_CACHE* registers only for Tegra20 [V6,19/27] PCI: tegra: Change PRSNT_SENSE IRQ log to debug [V6,20/27] PCI: tegra: Disable MSI for Tegra PCIe root port [V6,21/27] PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of soc struct [V6,22/27] dt-bindings: pci: tegra: Document PCIe DPD pinctrl optional prop [V6,23/27] arm64: tegra: Add PEX DPD states as pinctrl properties [V6,24/27] PCI: tegra: Put PEX CLK & BIAS pads in DPD mode [V6,25/27] PCI: Add DT binding for "reset-gpios" property [V6,26/27] PCI: tegra: Add support for GPIO based PERST# [V6,27/27] PCI: tegra: Change link retry log level to debug

Commit Message

Manikanta Maddireddy June 18, 2019, 6:02 p.m. UTC

Driver checks for link up three times before giving up, each retry attempt
is printed as an error. Letting users know that PCIe link is down and in the
process of being brought up again is for debug, not an error condition.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
---
V6: No change

V5: No change

V4: No change

V3: Changed dev_err to dev_dbg

V2: Updated commit log

 drivers/pci/controller/pci-tegra.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
index a819bc087a05..e95885a3bd67 100644
--- a/drivers/pci/controller/pci-tegra.c
+++ b/drivers/pci/controller/pci-tegra.c
@@ -2337,7 +2337,7 @@  static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
 		} while (--timeout);
 
 		if (!timeout) {
-			dev_err(dev, "link %u down, retrying\n", port->index);
+			dev_dbg(dev, "link %u down, retrying\n", port->index);
 			goto retry;
 		}