| Message ID | 20190718094718.25083-3-jonnyc@amazon.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | Amazon's Annapurna Labs DT-based PCIe host controller driver | expand |
On Thu, Jul 18, 2019 at 10:47:17, Jonathan Chocron <jonnyc@amazon.com> wrote: > Some PCIe controllers can be set to either Host or EP according to some > early boot FW. To make sure there is no discrepancy (e.g. FW configured > the port to EP mode while the DT specifies it as a host bridge or vice > versa), a check has been added for each mode. > > Signed-off-by: Jonathan Chocron <jonnyc@amazon.com> > --- > drivers/pci/controller/dwc/pcie-designware-ep.c | 8 ++++++++ > drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++++ > 2 files changed, 16 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c > index 2bf5a35c0570..00e59a134b93 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c > @@ -531,6 +531,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) > int ret; > u32 reg; > void *addr; > + u8 hdr_type; > unsigned int nbars; > unsigned int offset; > struct pci_epc *epc; > @@ -543,6 +544,13 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) > return -EINVAL; > } > > + hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE); > + if (hdr_type != PCI_HEADER_TYPE_NORMAL) { > + dev_err(pci->dev, "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n", > + hdr_type); > + return -EIO; > + } > + > ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows); > if (ret < 0) { > dev_err(dev, "Unable to read *num-ib-windows* property\n"); > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index f93252d0da5b..d2ca748e4c85 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -323,6 +323,7 @@ int dw_pcie_host_init(struct pcie_port *pp) > struct pci_bus *child; > struct pci_host_bridge *bridge; > struct resource *cfg_res; > + u8 hdr_type; > int ret; > > raw_spin_lock_init(&pci->pp.lock); > @@ -396,6 +397,13 @@ int dw_pcie_host_init(struct pcie_port *pp) > } > } > > + hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE); > + if (hdr_type != PCI_HEADER_TYPE_BRIDGE) { > + dev_err(pci->dev, "PCIe controller is not set to bridge type (hdr_type: 0x%x)!\n", > + hdr_type); > + return -EIO; > + } > + > pp->mem_base = pp->mem->start; > > if (!pp->va_cfg0_base) { > -- > 2.17.1 It doesn't harm. Thanks. Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 2bf5a35c0570..00e59a134b93 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -531,6 +531,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) int ret; u32 reg; void *addr; + u8 hdr_type; unsigned int nbars; unsigned int offset; struct pci_epc *epc; @@ -543,6 +544,13 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) return -EINVAL; } + hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE); + if (hdr_type != PCI_HEADER_TYPE_NORMAL) { + dev_err(pci->dev, "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n", + hdr_type); + return -EIO; + } + ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows); if (ret < 0) { dev_err(dev, "Unable to read *num-ib-windows* property\n"); diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index f93252d0da5b..d2ca748e4c85 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -323,6 +323,7 @@ int dw_pcie_host_init(struct pcie_port *pp) struct pci_bus *child; struct pci_host_bridge *bridge; struct resource *cfg_res; + u8 hdr_type; int ret; raw_spin_lock_init(&pci->pp.lock); @@ -396,6 +397,13 @@ int dw_pcie_host_init(struct pcie_port *pp) } } + hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE); + if (hdr_type != PCI_HEADER_TYPE_BRIDGE) { + dev_err(pci->dev, "PCIe controller is not set to bridge type (hdr_type: 0x%x)!\n", + hdr_type); + return -EIO; + } + pp->mem_base = pp->mem->start; if (!pp->va_cfg0_base) {
Some PCIe controllers can be set to either Host or EP according to some early boot FW. To make sure there is no discrepancy (e.g. FW configured the port to EP mode while the DT specifies it as a host bridge or vice versa), a check has been added for each mode. Signed-off-by: Jonathan Chocron <jonnyc@amazon.com> --- drivers/pci/controller/dwc/pcie-designware-ep.c | 8 ++++++++ drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++++ 2 files changed, 16 insertions(+)