| Message ID | 20190813025317.48290-1-xiaowei.bao@nxp.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | [PATCHv4,1/2] PCI: layerscape: Add the bar_fixed_64bit property in EP driver. | expand |
On 13/08/19 8:23 AM, Xiaowei Bao wrote: > The PCIe controller of layerscape just have 4 BARs, BAR0 and BAR1 > is 32bit, BAR3 and BAR4 is 64bit, this is determined by hardware, Do you mean BAR2 instead of BAR3 here? Thanks Kishon > so set the bar_fixed_64bit with 0x14. > > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> > --- > v2: > - Replace value 0x14 with a macro. > v3: > - No change. > v4: > - send the patch again with '--to'. > > drivers/pci/controller/dwc/pci-layerscape-ep.c | 1 + > 1 files changed, 1 insertions(+), 0 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c > index be61d96..227c33b 100644 > --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c > +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c > @@ -44,6 +44,7 @@ static int ls_pcie_establish_link(struct dw_pcie *pci) > .linkup_notifier = false, > .msi_capable = true, > .msix_capable = false, > + .bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4), > }; > > static const struct pci_epc_features* >
> -----Original Message----- > From: Kishon Vijay Abraham I <kishon@ti.com> > Sent: 2019年8月13日 12:36 > To: Xiaowei Bao <xiaowei.bao@nxp.com>; lorenzo.pieralisi@arm.com; > bhelgaas@google.com; M.h. Lian <minghuan.lian@nxp.com>; Mingkai Hu > <mingkai.hu@nxp.com>; Roy Zang <roy.zang@nxp.com>; > l.stach@pengutronix.de; tpiepho@impinj.com; Leonard Crestez > <leonard.crestez@nxp.com>; andrew.smirnov@gmail.com; > yue.wang@amlogic.com; hayashi.kunihiko@socionext.com; > dwmw@amazon.co.uk; jonnyc@amazon.com; linux-pci@vger.kernel.org; > linux-kernel@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; > linux-arm-kernel@lists.infradead.org > Subject: [EXT] Re: [PATCHv4 1/2] PCI: layerscape: Add the bar_fixed_64bit > property in EP driver. > > Caution: EXT Email > > On 13/08/19 8:23 AM, Xiaowei Bao wrote: > > The PCIe controller of layerscape just have 4 BARs, BAR0 and BAR1 is > > 32bit, BAR3 and BAR4 is 64bit, this is determined by hardware, > > Do you mean BAR2 instead of BAR3 here? Yes. > > Thanks > Kishon > > > so set the bar_fixed_64bit with 0x14. > > > > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> > > --- > > v2: > > - Replace value 0x14 with a macro. > > v3: > > - No change. > > v4: > > - send the patch again with '--to'. > > > > drivers/pci/controller/dwc/pci-layerscape-ep.c | 1 + > > 1 files changed, 1 insertions(+), 0 deletions(-) > > > > diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c > > b/drivers/pci/controller/dwc/pci-layerscape-ep.c > > index be61d96..227c33b 100644 > > --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c > > +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c > > @@ -44,6 +44,7 @@ static int ls_pcie_establish_link(struct dw_pcie *pci) > > .linkup_notifier = false, > > .msi_capable = true, > > .msix_capable = false, > > + .bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4), > > }; > > > > static const struct pci_epc_features* > >
diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c index be61d96..227c33b 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -44,6 +44,7 @@ static int ls_pcie_establish_link(struct dw_pcie *pci) .linkup_notifier = false, .msi_capable = true, .msix_capable = false, + .bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4), }; static const struct pci_epc_features*
The PCIe controller of layerscape just have 4 BARs, BAR0 and BAR1 is 32bit, BAR3 and BAR4 is 64bit, this is determined by hardware, so set the bar_fixed_64bit with 0x14. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> --- v2: - Replace value 0x14 with a macro. v3: - No change. v4: - send the patch again with '--to'. drivers/pci/controller/dwc/pci-layerscape-ep.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)