| Message ID | 20200213040644.45858-8-Zhiqiang.Hou@nxp.com (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Delegated to: | Lorenzo Pieralisi |
| Headers | show |
| Series | PCI: Recode Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs | expand |
On Thu, Feb 13, 2020 at 12:06:38PM +0800, Zhiqiang Hou wrote: > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > Allow the mobiveil_host_init() function to be used to re-init > host controller's PAB and GPEX CSR register block, as NXP > integrated Mobiveil IP has to reset and then re-init the PAB > and GPEX CSR registers upon hot-reset. > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in> Reviewed-by: Andrew Murray <amurray@thegoodpenguin.co.uk> > --- > V10: > - Refined the subject and change log. > > .../controller/mobiveil/pcie-mobiveil-host.c | 19 ++++++++++++------- > .../pci/controller/mobiveil/pcie-mobiveil.h | 1 + > 2 files changed, 13 insertions(+), 7 deletions(-) > > diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c > index 53ab8412a1de..44dd641fede3 100644 > --- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c > +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c > @@ -221,18 +221,23 @@ static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie) > writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET); > } > > -static int mobiveil_host_init(struct mobiveil_pcie *pcie) > +int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit) > { > struct mobiveil_root_port *rp = &pcie->rp; > struct pci_host_bridge *bridge = rp->bridge; > u32 value, pab_ctrl, type; > struct resource_entry *win; > > - /* setup bus numbers */ > - value = mobiveil_csr_readl(pcie, PCI_PRIMARY_BUS); > - value &= 0xff000000; > - value |= 0x00ff0100; > - mobiveil_csr_writel(pcie, value, PCI_PRIMARY_BUS); > + pcie->ib_wins_configured = 0; > + pcie->ob_wins_configured = 0; > + > + if (!reinit) { > + /* setup bus numbers */ > + value = mobiveil_csr_readl(pcie, PCI_PRIMARY_BUS); > + value &= 0xff000000; > + value |= 0x00ff0100; > + mobiveil_csr_writel(pcie, value, PCI_PRIMARY_BUS); > + } > > /* > * program Bus Master Enable Bit in Command Register in PAB Config > @@ -576,7 +581,7 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) > * configure all inbound and outbound windows and prepare the RC for > * config access > */ > - ret = mobiveil_host_init(pcie); > + ret = mobiveil_host_init(pcie, false); > if (ret) { > dev_err(dev, "Failed to initialize host\n"); > return ret; > diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h > index 346bf79a581b..623c5f0c4441 100644 > --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h > +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h > @@ -166,6 +166,7 @@ struct mobiveil_pcie { > }; > > int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie); > +int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit); > bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie); > int mobiveil_bringup_link(struct mobiveil_pcie *pcie); > void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr, > -- > 2.17.1 >
Hi Andrew, Thanks a lot for your review! Thanks, Zhiqiang > -----Original Message----- > From: Andrew Murray <amurray@thegoodpenguin.co.uk> > Sent: 2020年2月21日 1:29 > To: Z.q. Hou <zhiqiang.hou@nxp.com> > Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; > bhelgaas@google.com; robh+dt@kernel.org; andrew.murray@arm.com; > arnd@arndb.de; mark.rutland@arm.com; l.subrahmanya@mobiveil.co.in; > shawnguo@kernel.org; m.karthikeyan@mobiveil.co.in; Leo Li > <leoyang.li@nxp.com>; lorenzo.pieralisi@arm.com; > catalin.marinas@arm.com; will.deacon@arm.com; Mingkai Hu > <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>; Xiaowei Bao > <xiaowei.bao@nxp.com> > Subject: Re: [PATCHv10 07/13] PCI: mobiveil: Allow mobiveil_host_init() to > be used to re-init host > > On Thu, Feb 13, 2020 at 12:06:38PM +0800, Zhiqiang Hou wrote: > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > > Allow the mobiveil_host_init() function to be used to re-init host > > controller's PAB and GPEX CSR register block, as NXP integrated > > Mobiveil IP has to reset and then re-init the PAB and GPEX CSR > > registers upon hot-reset. > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in> > > Reviewed-by: Andrew Murray <amurray@thegoodpenguin.co.uk> > > > --- > > V10: > > - Refined the subject and change log. > > > > .../controller/mobiveil/pcie-mobiveil-host.c | 19 ++++++++++++------- > > .../pci/controller/mobiveil/pcie-mobiveil.h | 1 + > > 2 files changed, 13 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c > > b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c > > index 53ab8412a1de..44dd641fede3 100644 > > --- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c > > +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c > > @@ -221,18 +221,23 @@ static void mobiveil_pcie_enable_msi(struct > mobiveil_pcie *pcie) > > writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET); } > > > > -static int mobiveil_host_init(struct mobiveil_pcie *pcie) > > +int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit) > > { > > struct mobiveil_root_port *rp = &pcie->rp; > > struct pci_host_bridge *bridge = rp->bridge; > > u32 value, pab_ctrl, type; > > struct resource_entry *win; > > > > - /* setup bus numbers */ > > - value = mobiveil_csr_readl(pcie, PCI_PRIMARY_BUS); > > - value &= 0xff000000; > > - value |= 0x00ff0100; > > - mobiveil_csr_writel(pcie, value, PCI_PRIMARY_BUS); > > + pcie->ib_wins_configured = 0; > > + pcie->ob_wins_configured = 0; > > + > > + if (!reinit) { > > + /* setup bus numbers */ > > + value = mobiveil_csr_readl(pcie, PCI_PRIMARY_BUS); > > + value &= 0xff000000; > > + value |= 0x00ff0100; > > + mobiveil_csr_writel(pcie, value, PCI_PRIMARY_BUS); > > + } > > > > /* > > * program Bus Master Enable Bit in Command Register in PAB Config > > @@ -576,7 +581,7 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie > *pcie) > > * configure all inbound and outbound windows and prepare the RC for > > * config access > > */ > > - ret = mobiveil_host_init(pcie); > > + ret = mobiveil_host_init(pcie, false); > > if (ret) { > > dev_err(dev, "Failed to initialize host\n"); > > return ret; > > diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h > > b/drivers/pci/controller/mobiveil/pcie-mobiveil.h > > index 346bf79a581b..623c5f0c4441 100644 > > --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h > > +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h > > @@ -166,6 +166,7 @@ struct mobiveil_pcie { }; > > > > int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie); > > +int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit); > > bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie); int > > mobiveil_bringup_link(struct mobiveil_pcie *pcie); void > > program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 > > cpu_addr, > > -- > > 2.17.1 > >
diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c index 53ab8412a1de..44dd641fede3 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c @@ -221,18 +221,23 @@ static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie) writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET); } -static int mobiveil_host_init(struct mobiveil_pcie *pcie) +int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit) { struct mobiveil_root_port *rp = &pcie->rp; struct pci_host_bridge *bridge = rp->bridge; u32 value, pab_ctrl, type; struct resource_entry *win; - /* setup bus numbers */ - value = mobiveil_csr_readl(pcie, PCI_PRIMARY_BUS); - value &= 0xff000000; - value |= 0x00ff0100; - mobiveil_csr_writel(pcie, value, PCI_PRIMARY_BUS); + pcie->ib_wins_configured = 0; + pcie->ob_wins_configured = 0; + + if (!reinit) { + /* setup bus numbers */ + value = mobiveil_csr_readl(pcie, PCI_PRIMARY_BUS); + value &= 0xff000000; + value |= 0x00ff0100; + mobiveil_csr_writel(pcie, value, PCI_PRIMARY_BUS); + } /* * program Bus Master Enable Bit in Command Register in PAB Config @@ -576,7 +581,7 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) * configure all inbound and outbound windows and prepare the RC for * config access */ - ret = mobiveil_host_init(pcie); + ret = mobiveil_host_init(pcie, false); if (ret) { dev_err(dev, "Failed to initialize host\n"); return ret; diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h index 346bf79a581b..623c5f0c4441 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h @@ -166,6 +166,7 @@ struct mobiveil_pcie { }; int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie); +int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit); bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie); int mobiveil_bringup_link(struct mobiveil_pcie *pcie); void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,