@@ -1045,6 +1045,27 @@
/* PCIe Designated Vendor-Specific Capability */
#define PCI_DVSEC_HEADER1 4 /* Designated Vendor-Specific Header 1 */
#define PCI_DVSEC_HEADER2 8 /* Designated Vendor-Specific Header 2 */
+#define PCI_DVSEC_INTEL_CXL 0 /* Designated Vendor-Specific ID for Intel CXL */
+#define PCI_DVSEC_VENDOR_ID_CXL 0x1e98 /* Designated Vendor-Specific Vendor ID for CXL */
+
+/* PCIe CXL Designated Vendor-Specific Capabilities, Control, Status */
+#define PCI_CXL_CAP 0x0a /* CXL Capability Register */
+#define PCI_CXL_CAP_CACHE 0x0001 /* CXL.cache Protocol Support */
+#define PCI_CXL_CAP_IO 0x0002 /* CXL.io Protocol Support */
+#define PCI_CXL_CAP_MEM 0x0004 /* CXL.mem Protocol Support */
+#define PCI_CXL_CAP_MEM_HWINIT 0x0008 /* CXL.mem Initalizes with HW/FW Support */
+#define PCI_CXL_CAP_HDM_CNT(x) (((x) & (3 << 4)) >> 4) /* CXL Number of HDM ranges */
+#define PCI_CXL_CAP_VIRAL 0x4000 /* CXL Viral Handling Support */
+#define PCI_CXL_CTRL 0x0c /* CXL Control Register */
+#define PCI_CXL_CTRL_CACHE 0x0001 /* CXL.cache Protocol Enable */
+#define PCI_CXL_CTRL_IO 0x0002 /* CXL.io Protocol Enable */
+#define PCI_CXL_CTRL_MEM 0x0004 /* CXL.mem Protocol Enable */
+#define PCI_CXL_CTRL_CACHE_SF_COV(x) (((x) & (0x1f << 3)) >> 3) /* Snoop Filter Coverage */
+#define PCI_CXL_CTRL_CACHE_SF_GRAN(x) (((x) & (0x7 << 8)) >> 8) /* Snoop Filter Granularity */
+#define PCI_CXL_CTRL_CACHE_CLN 0x0800 /* CXL.cache Performance Hint on Clean Evictions */
+#define PCI_CXL_CTRL_VIRAL 0x4000 /* CXL Viral Handling Enable */
+#define PCI_CXL_STATUS 0x0e /* CXL Status Register */
+#define PCI_CXL_STATUS_VIRAL 0x4000 /* CXL Viral Handling Status */
/* Access Control Services */
#define PCI_ACS_CAP 0x04 /* ACS Capability Register */
@@ -634,6 +634,57 @@ cap_rclink(struct device *d, int where)
}
}
+static void
+cap_cxl(struct device *d, int where)
+{
+ u16 l;
+
+ printf("CXL Designated Vendor-Specific:\n");
+ if (verbose < 2)
+ return;
+
+ if (!config_fetch(d, where + PCI_CXL_CAP, 12))
+ return;
+
+ l = get_conf_word(d, where + PCI_CXL_CAP);
+ printf("\t\tCXLCap:\tCache%c IO%c Mem%c Mem HW Init%c HDMCount %d Viral%c\n",
+ FLAG(l, PCI_CXL_CAP_CACHE), FLAG(l, PCI_CXL_CAP_IO), FLAG(l, PCI_CXL_CAP_MEM),
+ FLAG(l, PCI_CXL_CAP_MEM_HWINIT), PCI_CXL_CAP_HDM_CNT(l), FLAG(l, PCI_CXL_CAP_VIRAL));
+
+ l = get_conf_word(d, where + PCI_CXL_CTRL);
+ printf("\t\tCXLCtl:\tCache%c IO%c Mem%c Cache SF Cov %d Cache SF Gran %d Cache Clean%c Viral%c\n",
+ FLAG(l, PCI_CXL_CTRL_CACHE), FLAG(l, PCI_CXL_CTRL_IO), FLAG(l, PCI_CXL_CTRL_MEM),
+ PCI_CXL_CTRL_CACHE_SF_COV(l), PCI_CXL_CTRL_CACHE_SF_GRAN(l), FLAG(l, PCI_CXL_CTRL_CACHE_CLN),
+ FLAG(l, PCI_CXL_CTRL_VIRAL));
+
+ l = get_conf_word(d, where + PCI_CXL_STATUS);
+ printf("\t\tCXLSta:\tViral%c\n", FLAG(l, PCI_CXL_STATUS_VIRAL));
+}
+
+static int
+is_cxl_cap(struct device *d, int where)
+{
+ u32 hdr;
+ u16 w;
+
+ if (!config_fetch(d, where + PCI_DVSEC_HEADER1, 8))
+ return 0;
+
+ /* Check for supported Vendor */
+ hdr = get_conf_long(d, where + PCI_DVSEC_HEADER1);
+ w = BITS(hdr, 0, 16);
+ if (w != PCI_DVSEC_VENDOR_ID_CXL)
+ return 0;
+
+ /* Check for Designated Vendor-Specific ID */
+ hdr = get_conf_long(d, where + PCI_DVSEC_HEADER2);
+ w = BITS(hdr, 0, 16);
+ if (w == PCI_DVSEC_INTEL_CXL)
+ return 1;
+
+ return 0;
+}
+
static void
cap_dvsec(struct device *d, int where)
{
@@ -947,7 +998,10 @@ show_ext_caps(struct device *d, int type)
printf("Readiness Time Reporting <?>\n");
break;
case PCI_EXT_CAP_ID_DVSEC:
- cap_dvsec(d, where);
+ if (is_cxl_cap(d, where))
+ cap_cxl(d, where);
+ else
+ cap_dvsec(d, where);
break;
case PCI_EXT_CAP_ID_VF_REBAR:
printf("VF Resizable BAR <?>\n");
new file mode 100644
@@ -0,0 +1,340 @@
+6b:00.0 Unassigned class [ff00]: Intel Corporation Device 0d93
+ Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Interrupt: pin A routed to IRQ 255
+ NUMA node: 0
+ Region 0: Memory at b3100000 (32-bit, non-prefetchable) [disabled] [size=1M]
+ Region 2: I/O ports at a400 [disabled] [size=1K]
+ Region 4: Memory at b1000000 (32-bit, prefetchable) [disabled] [size=16M]
+ Capabilities: [40] Express (v2) Root Complex Integrated Endpoint, MSI 00
+ DevCap: MaxPayload 256 bytes, PhantFunc 0
+ ExtTag+ RBE+ FLReset+
+ DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+
+ RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop- FLReset-
+ MaxPayload 128 bytes, MaxReadReq 512 bytes
+ DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
+ DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, NROPrPrP-, LTR+
+ 10BitTagComp-, 10BitTagReq-, OBFF Via WAKE#, ExtFmt+, EETLPPrefix+, MaxEETLPPrefixes 1
+ EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
+ FRS-
+ AtomicOpsCap: 32bit+ 64bit+ 128bitCAS+
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
+ AtomicOpsCtl: ReqEn-
+ Capabilities: [80] MSI: Enable- Count=1/4 Maskable+ 64bit+
+ Address: 0000000000000000 Data: 0000
+ Masking: 00000000 Pending: 00000000
+ Capabilities: [a0] Power Management version 3
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
+ Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [100 v1] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-
+ UESvrt: DLP+ SDES- TLP+ FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
+ AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn+ ECRCChkCap+ ECRCChkEn+
+ MultHdrRecCap+ MultHdrRecEn- TLPPfxPres- HdrLogCap-
+ HeaderLog: 00000000 00000000 00000000 00000000
+ Capabilities: [200 v1] Multi-Function Virtual Channel <?>
+ Capabilities: [300 v1] Virtual Channel
+ Caps: LPEVC=0 RefClk=100ns PATEntryBits=1
+ Arb: Fixed- WRR32- WRR64- WRR128-
+ Ctrl: ArbSelect=Fixed
+ Status: InProgress-
+ VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
+ Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
+ Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
+ Status: NegoPending- InProgress-
+ Capabilities: [550 v1] Multicast
+ McastCap: MaxGroups 64, WindowSz 1 (2 bytes) McastCtl: NumGroups 1, Enable-
+ McastBAR: IndexPos 0, BaseAddr 0000000000000000
+ McastReceiveVec: 0000000000000000
+ McastBlockAllVec: 0000000000000000
+ McastBlockUntransVec: 0000000000000000
+ Capabilities: [588 v1] Latency Tolerance Reporting
+ Max snoop latency: 0ns
+ Max no snoop latency: 0ns
+ Capabilities: [5b0 v1] Transaction Processing Hints
+ Extended requester support
+ Steering table in TPH capability structure
+ Capabilities: [6e0 v1] Address Translation Service (ATS)
+ ATSCap: Invalidate Queue Depth: 00
+ ATSCtl: Enable-, Smallest Translation Unit: 00
+ Capabilities: [700 v1] Resizable BAR <?>
+ Capabilities: [714 v1] Secondary PCI Express
+ LnkCtl3: LnkEquIntrruptEn-, PerformEqu-
+ LaneErrStat: 0
+ Capabilities: [b20 v1] Page Request Interface (PRI)
+ PRICtl: Enable- Reset-
+ PRISta: RF- UPRGI- Stopped+
+ Page Request Capacity: 00000000, Page Request Allocation: 00000000
+ Capabilities: [b40 v1] Process Address Space ID (PASID)
+ PASIDCap: Exec+ Priv+, Max PASID Width: 14
+ PASIDCtl: Enable- Exec- Priv-
+ Capabilities: [b50 v1] Precision Time Measurement
+ PTMCap: Requester:- Responder:- Root:-
+ PTMClockGranularity: Unimplemented
+ PTMControl: Enabled:- RootSelected:-
+ PTMEffectiveGranularity: Unknown
+ Capabilities: [d00 v1] Vendor Specific Information: ID=0040 Rev=1 Len=04c <?>
+ Capabilities: [e00 v1] CXL Designated Vendor-Specific:
+ CXLCap: Cache+ IO+ Mem+ Mem HW Init+ HDMCount 1 Viral-
+ CXLCtl: Cache+ IO+ Mem- Cache SF Cov 0 Cache SF Gran 0 Cache Clean- Viral-
+ CXLSta: Viral-
+ Capabilities: [e38 v1] Device Serial Number 12-34-56-78-90-00-00-00
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Compute eXpress Link[1] is a new CPU interconnect created with workload accelerators in mind. The interconnect relies on PCIe electrical and physical interconnect for communication via a Flex Bus port which allows designs to choose between providing PCIe or CXL. This patch introduces basic support for lspci decode of CXL and builds upon the existing Designated Vendor-Specific support in lspci through identification of a supporting CXL device using DVSEC Vendor ID and DVSEC ID. [1] https://www.computeexpresslink.org/ Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com> --- lib/header.h | 21 +++ ls-ecaps.c | 56 +++++++- tests/cap-dvsec-cxl | 340 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 416 insertions(+), 1 deletion(-) create mode 100644 tests/cap-dvsec-cxl