Message ID | 20200624040024.895996-1-sean.v.kelley@linux.intel.com (mailing list archive) |
---|---|
State | Superseded, archived |
Headers | show |
Series | [v2] pciutils: Add decode support for RCECs | expand |
On Tue, Jun 23, 2020 at 09:00:24PM -0700, Sean V Kelley wrote: > Root Complex Event Collectors provide support for terminating error > and PME messages from RCiEPs. This patch provides basic decoding for > the lspci RCEC Endpoint Association Extended Capability. See PCIe 5.0-1, > sec 7.9.10 for further details. > > Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com> Looks good to me. Minor comments below, but either way: Reviewed-by: Bjorn Helgaas <bhelgaas@google.com> > --- > Changes since v1 [1]: > > - Corrections to commit log wording/abbreviation. > - Added mention of Endpoint Association for clarity. > - Removed "Desc:" from output as not necessary. > - Removed "cap_ver" from output as redundant. > - Broke out RCiEP device numbers as a comma separated list. > (Bjorn Helgaas) > > [1] https://lore.kernel.org/linux-pci/20200622230330.799259-1-sean.v.kelley@linux.intel.com/ > > Thanks, > > Sean > --- > lib/header.h | 8 +- > ls-ecaps.c | 50 ++++++++- > setpci.c | 2 +- > tests/cap-rcec | 299 +++++++++++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 355 insertions(+), 4 deletions(-) > create mode 100644 tests/cap-rcec > > diff --git a/lib/header.h b/lib/header.h > index 472816e..57a9343 100644 > --- a/lib/header.h > +++ b/lib/header.h > @@ -219,7 +219,7 @@ > #define PCI_EXT_CAP_ID_PB 0x04 /* Power Budgeting */ > #define PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */ > #define PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declaration */ > -#define PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */ > +#define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */ > #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */ > #define PCI_EXT_CAP_ID_VC2 0x09 /* Virtual Channel (2nd ID) */ > #define PCI_EXT_CAP_ID_RCRB 0x0a /* Root Complex Register Block */ > @@ -1048,6 +1048,12 @@ > #define PCI_RCLINK_LINK_ADDR 8 /* Link Entry: Address (64-bit) */ > #define PCI_RCLINK_LINK_SIZE 16 /* Link Entry: sizeof */ > > +/* Root Complex Event Collector Endpoint Association */ > +#define PCI_RCEC_EP_CAP_VER(reg) (((reg) >> 16) & 0xf) > +#define PCI_RCEC_BUSN_REG_VER 0x02 /* as per PCIe sec 7.9.10.1 */ > +#define PCI_RCEC_RCIEP_BMAP 0x0004 /* as per PCIe sec 7.9.10.2 */ > +#define PCI_RCEC_BUSN_REG 0x0008 /* as per PCIe sec 7.9.10.3 */ > + > /* PCIe Vendor-Specific Capability */ > #define PCI_EVNDR_HEADER 4 /* Vendor-Specific Header */ > #define PCI_EVNDR_REGISTERS 8 /* Vendor-Specific Registers */ > diff --git a/ls-ecaps.c b/ls-ecaps.c > index e71209e..ae26393 100644 > --- a/ls-ecaps.c > +++ b/ls-ecaps.c > @@ -634,6 +634,52 @@ cap_rclink(struct device *d, int where) > } > } > > +static void > +cap_rcec(struct device *d, int where) > +{ > + printf("Root Complex Event Collector Endpoint Association\n"); > + if (verbose < 2) > + return; > + > + if (!config_fetch(d, where, 12)) > + return; > + > + u32 hdr = get_conf_long(d, where); > + byte cap_ver = PCI_RCEC_EP_CAP_VER(hdr); > + u32 bmap = get_conf_long(d, where + PCI_RCEC_RCIEP_BMAP); > + printf("\t\tRCiEPBitmap: "); > + if (bmap) > + { > + int dev=0; > + int prevmatched=0; > + printf("RCiEP at Device(s):"); > + while (bmap) > + { > + if (BITS(bmap, 0, 1)) > + if (!prevmatched) > + { > + prevmatched=1; > + printf(" %u", dev); > + } > + else > + printf("%s %u", (prevmatched) ? "," : "", dev); Maybe this could be done in one printf? if (bmap) { int prevmatched = 0; for (dev = 0; dev < 32; dev++) if (BITS(bmap, dev, 1)) { printf("%s%u", prevmatched ? ", " : "", dev); prevmatched = 1; } } > + bmap >>= 1; > + dev += 1; > + } > + } > + else > + printf("00000000"); Or "[none]", with "00000000 [none]" for the "-vvv" case? Seems like an RCEC with no associated devices wouldn't be very useful. Although I guess it could have devices on other buses. > + printf("\n"); > + > + if (cap_ver < PCI_RCEC_BUSN_REG_VER) > + return; > + > + u32 busn = get_conf_long(d, where + PCI_RCEC_BUSN_REG); > + printf("\t\tRCECLastBus=%02x RCECFirstBus=%02x\n", > + BITS(busn, 16, 8), > + BITS(busn, 8, 8)); The spec term is "RCEC *Next* Bus", not "RCEC First Bus". Maybe print these in the "Next Last" order so it comes out like a bus number range when enabled? The example below ("RCECLastBus=00 RCECFirstBus=ff") is actually the case when there are no additional bus numbers associated with this RCEC. show_range() handles a similar case by printing "[disabled]" (as well as the raw numbers in the "enabled" or "verbose > 2" cases). "[disabled]" wouldn't be quite right here, but maybe "[none]"? Could be AssociatedBusNumbers: 01-07 AssociatedBusNumbers: [none] # -vv case AssociatedBusNumbers: ff-00 [none] # -vvv case But maybe that's applying too much interpretation. We don't do anything so fancy for bridge secondary/subordinate bus numbers, for example. > +} > + > static void > cap_dvsec_cxl(struct device *d, int where) > { > @@ -991,8 +1037,8 @@ show_ext_caps(struct device *d, int type) > case PCI_EXT_CAP_ID_RCILINK: > printf("Root Complex Internal Link <?>\n"); > break; > - case PCI_EXT_CAP_ID_RCECOLL: > - printf("Root Complex Event Collector <?>\n"); > + case PCI_EXT_CAP_ID_RCEC: > + cap_rcec(d, where); > break; > case PCI_EXT_CAP_ID_MFVC: > printf("Multi-Function Virtual Channel <?>\n"); > diff --git a/setpci.c b/setpci.c > index 90ca726..2cb70fa 100644 > --- a/setpci.c > +++ b/setpci.c > @@ -350,7 +350,7 @@ static const struct reg_name pci_reg_names[] = { > { 0x20004, 0, 0, "ECAP_PB" }, > { 0x20005, 0, 0, "ECAP_RCLINK" }, > { 0x20006, 0, 0, "ECAP_RCILINK" }, > - { 0x20007, 0, 0, "ECAP_RCECOLL" }, > + { 0x20007, 0, 0, "ECAP_RCEC" }, > { 0x20008, 0, 0, "ECAP_MFVC" }, > { 0x20009, 0, 0, "ECAP_VC2" }, > { 0x2000a, 0, 0, "ECAP_RBCB" }, > diff --git a/tests/cap-rcec b/tests/cap-rcec > new file mode 100644 > index 0000000..4196228 > --- /dev/null > +++ b/tests/cap-rcec > @@ -0,0 +1,299 @@ > +6a:00.4 Generic system peripheral [0807]: Intel Corporation Device 0b23 > + Subsystem: Intel Corporation Device 0000 > + Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- > + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- > + Interrupt: pin A routed to IRQ 255 > + NUMA node: 0 > + Capabilities: [40] Express (v2) Root Complex Event Collector, MSI 00 > + DevCap: MaxPayload 512 bytes, PhantFunc 0 > + ExtTag- RBE- > + DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq- > + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- > + MaxPayload 128 bytes, MaxReadReq 128 bytes > + DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend- > + RootCap: CRSVisible- > + RootCtl: ErrCorrectable+ ErrNon-Fatal+ ErrFatal+ PMEIntEna- CRSVisible- > + RootSta: PME ReqID 0000, PMEStatus- PMEPending- > + DevCap2: Completion Timeout: Not Supported, TimeoutDis- NROPrPrP- LTR- > + 10BitTagComp- 10BitTagReq- OBFF Not Supported, ExtFmt- EETLPPrefix- > + EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit- > + FRS- > + DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LTR- OBFF Disabled, > + Capabilities: [80] Power Management version 3 > + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) > + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- > + Capabilities: [90] MSI: Enable- Count=1/1 Maskable+ 64bit- > + Address: 00000000 Data: 0000 > + Masking: 00000000 Pending: 00000000 > + Capabilities: [100 v1] Advanced Error Reporting > + UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- > + UEMsk: DLP- SDES+ TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol- > + UESvrt: DLP+ SDES- TLP+ FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- > + CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- > + CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ > + AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- > + MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- > + HeaderLog: 00000000 00000000 00000000 00000000 > + RootCmd: CERptEn- NFERptEn- FERptEn- > + RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd- > + FirstFatal- NonFatalMsg- FatalMsg- IntMsg 0 > + ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000 > + Capabilities: [160 v2] Root Complex Event Collector Endpoint Association > + RCiEPBitmap: RCiEP at Device(s): 0, 1, 4, 7, 8, 9, 10, 12, 13 > + RCECLastBus=00 RCECFirstBus=ff > +00: 86 80 23 0b 00 01 10 00 00 00 07 08 00 00 00 00 > +10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > +20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 00 00 > +30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 01 00 00 > +40: 10 80 a2 00 02 00 00 00 07 00 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00 00 00 00 00 00 00 00 > +ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > -- > 2.27.0 >
On Wed, 2020-06-24 at 10:57 -0500, Bjorn Helgaas wrote: > On Tue, Jun 23, 2020 at 09:00:24PM -0700, Sean V Kelley wrote: > > Root Complex Event Collectors provide support for terminating error > > and PME messages from RCiEPs. This patch provides basic decoding > > for > > the lspci RCEC Endpoint Association Extended Capability. See PCIe > > 5.0-1, > > sec 7.9.10 for further details. > > > > Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com> > > Looks good to me. Minor comments below, but either way: > > Reviewed-by: Bjorn Helgaas <bhelgaas@google.com> > > > --- > > Changes since v1 [1]: > > > > - Corrections to commit log wording/abbreviation. > > - Added mention of Endpoint Association for clarity. > > - Removed "Desc:" from output as not necessary. > > - Removed "cap_ver" from output as redundant. > > - Broke out RCiEP device numbers as a comma separated list. > > (Bjorn Helgaas) > > > > [1] > > https://lore.kernel.org/linux-pci/20200622230330.799259-1-sean.v.kelley@linux.intel.com/ > > > > Thanks, > > > > Sean > > --- > > lib/header.h | 8 +- > > ls-ecaps.c | 50 ++++++++- > > setpci.c | 2 +- > > tests/cap-rcec | 299 > > +++++++++++++++++++++++++++++++++++++++++++++++++ > > 4 files changed, 355 insertions(+), 4 deletions(-) > > create mode 100644 tests/cap-rcec > > > > diff --git a/lib/header.h b/lib/header.h > > index 472816e..57a9343 100644 > > --- a/lib/header.h > > +++ b/lib/header.h > > @@ -219,7 +219,7 @@ > > #define PCI_EXT_CAP_ID_PB 0x04 /* Power Budgeting */ > > #define PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex > > Link Declaration */ > > #define PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex > > Internal Link Declaration */ > > -#define PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex > > Event Collector */ > > +#define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex > > Event Collector */ > > #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function > > Virtual Channel */ > > #define PCI_EXT_CAP_ID_VC2 0x09 /* Virtual Channel (2nd ID) > > */ > > #define PCI_EXT_CAP_ID_RCRB 0x0a /* Root Complex > > Register Block */ > > @@ -1048,6 +1048,12 @@ > > #define PCI_RCLINK_LINK_ADDR 8 /* Link Entry: Address (64- > > bit) */ > > #define PCI_RCLINK_LINK_SIZE 16 /* Link Entry: sizeof */ > > > > +/* Root Complex Event Collector Endpoint Association */ > > +#define PCI_RCEC_EP_CAP_VER(reg) (((reg) >> 16) & 0xf) > > +#define PCI_RCEC_BUSN_REG_VER 0x02 /* as per PCIe sec > > 7.9.10.1 */ > > +#define PCI_RCEC_RCIEP_BMAP 0x0004 /* as per PCIe sec > > 7.9.10.2 */ > > +#define PCI_RCEC_BUSN_REG 0x0008 /* as per PCIe sec 7.9.10.3 > > */ > > + > > /* PCIe Vendor-Specific Capability */ > > #define PCI_EVNDR_HEADER 4 /* Vendor-Specific Header */ > > #define PCI_EVNDR_REGISTERS 8 /* Vendor-Specific > > Registers */ > > diff --git a/ls-ecaps.c b/ls-ecaps.c > > index e71209e..ae26393 100644 > > --- a/ls-ecaps.c > > +++ b/ls-ecaps.c > > @@ -634,6 +634,52 @@ cap_rclink(struct device *d, int where) > > } > > } > > > > +static void > > +cap_rcec(struct device *d, int where) > > +{ > > + printf("Root Complex Event Collector Endpoint Association\n"); > > + if (verbose < 2) > > + return; > > + > > + if (!config_fetch(d, where, 12)) > > + return; > > + > > + u32 hdr = get_conf_long(d, where); > > + byte cap_ver = PCI_RCEC_EP_CAP_VER(hdr); > > + u32 bmap = get_conf_long(d, where + PCI_RCEC_RCIEP_BMAP); > > + printf("\t\tRCiEPBitmap: "); > > + if (bmap) > > + { > > + int dev=0; > > + int prevmatched=0; > > + printf("RCiEP at Device(s):"); > > + while (bmap) > > + { > > + if (BITS(bmap, 0, 1)) > > + if (!prevmatched) > > + { > > + prevmatched=1; > > + printf(" %u", dev); > > + } > > + else > > + printf("%s %u", (prevmatched) ? "," : "", dev); > > Maybe this could be done in one printf? > > if (bmap) > { > int prevmatched = 0; > > for (dev = 0; dev < 32; dev++) > if (BITS(bmap, dev, 1)) > { > printf("%s%u", prevmatched ? ", " : "", dev); > prevmatched = 1; > } > } That works well, I can also add the hyphen if it is adjacent with this, I think: for (int dev=0; dev < 32; dev++) { if (BITS(bmap, dev, 1)) { if (!adjcount) printf("%s %u", (prevmatched) ? "," : "", dev); prevmatched=1; adjcount++; prevdev=dev; } else { if (adjcount > 1) printf("-%u", prevdev); adjacent=0; } } > > + bmap >>= 1; > > + dev += 1; > > + } > > + } > > + else > > + printf("00000000"); > > Or "[none]", with "00000000 [none]" for the "-vvv" case? Seems like > an > RCEC with no associated devices wouldn't be very useful. Although I > guess it could have devices on other buses. > It's more informative to note that it really means "none". Will do. > > + printf("\n"); > > + > > + if (cap_ver < PCI_RCEC_BUSN_REG_VER) > > + return; > > + > > + u32 busn = get_conf_long(d, where + PCI_RCEC_BUSN_REG); > > + printf("\t\tRCECLastBus=%02x RCECFirstBus=%02x\n", > > + BITS(busn, 16, 8), > > + BITS(busn, 8, 8)); > > The spec term is "RCEC *Next* Bus", not "RCEC First Bus". > > Maybe print these in the "Next Last" order so it comes out like a bus > number range when enabled? Good catch, I'm not sure where I was getting First... And I think the bus number range with Next Last order makes sense. > > The example below ("RCECLastBus=00 RCECFirstBus=ff") is actually the > case when there are no additional bus numbers associated with this > RCEC. show_range() handles a similar case by printing "[disabled]" > (as well as the raw numbers in the "enabled" or "verbose > 2" cases). > "[disabled]" wouldn't be quite right here, but maybe "[none]"? > > Could be > > AssociatedBusNumbers: 01-07 > AssociatedBusNumbers: [none] # -vv case > AssociatedBusNumbers: ff-00 [none] # -vvv case No one seems to use 'verbose' very effectively for individual caps in ls-ecaps, afaict. It's either on/off so to speak. I really like this granularity, however. I'll have a look. Thanks, Sean > > But maybe that's applying too much interpretation. We don't do > anything so fancy for bridge secondary/subordinate bus numbers, for > example. > > > +} > > + > > static void > > cap_dvsec_cxl(struct device *d, int where) > > { > > @@ -991,8 +1037,8 @@ show_ext_caps(struct device *d, int type) > > case PCI_EXT_CAP_ID_RCILINK: > > printf("Root Complex Internal Link <?>\n"); > > break; > > - case PCI_EXT_CAP_ID_RCECOLL: > > - printf("Root Complex Event Collector <?>\n"); > > + case PCI_EXT_CAP_ID_RCEC: > > + cap_rcec(d, where); > > break; > > case PCI_EXT_CAP_ID_MFVC: > > printf("Multi-Function Virtual Channel <?>\n"); > > diff --git a/setpci.c b/setpci.c > > index 90ca726..2cb70fa 100644 > > --- a/setpci.c > > +++ b/setpci.c > > @@ -350,7 +350,7 @@ static const struct reg_name pci_reg_names[] = > > { > > { 0x20004, 0, 0, "ECAP_PB" }, > > { 0x20005, 0, 0, "ECAP_RCLINK" }, > > { 0x20006, 0, 0, "ECAP_RCILINK" }, > > - { 0x20007, 0, 0, "ECAP_RCECOLL" }, > > + { 0x20007, 0, 0, "ECAP_RCEC" }, > > { 0x20008, 0, 0, "ECAP_MFVC" }, > > { 0x20009, 0, 0, "ECAP_VC2" }, > > { 0x2000a, 0, 0, "ECAP_RBCB" }, > > diff --git a/tests/cap-rcec b/tests/cap-rcec > > new file mode 100644 > > index 0000000..4196228 > > --- /dev/null > > +++ b/tests/cap-rcec > > @@ -0,0 +1,299 @@ > > +6a:00.4 Generic system peripheral [0807]: Intel Corporation Device > > 0b23 > > + Subsystem: Intel Corporation Device 0000 > > + Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- > > VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- > > + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast > > >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- > > + Interrupt: pin A routed to IRQ 255 > > + NUMA node: 0 > > + Capabilities: [40] Express (v2) Root Complex Event > > Collector, MSI 00 > > + DevCap: MaxPayload 512 bytes, PhantFunc 0 > > + ExtTag- RBE- > > + DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq- > > + RlxdOrd- ExtTag- PhantFunc- AuxPwr- > > NoSnoop- > > + MaxPayload 128 bytes, MaxReadReq 128 bytes > > + DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- > > AuxPwr- TransPend- > > + RootCap: CRSVisible- > > + RootCtl: ErrCorrectable+ ErrNon-Fatal+ ErrFatal+ > > PMEIntEna- CRSVisible- > > + RootSta: PME ReqID 0000, PMEStatus- PMEPending- > > + DevCap2: Completion Timeout: Not Supported, > > TimeoutDis- NROPrPrP- LTR- > > + 10BitTagComp- 10BitTagReq- OBFF Not > > Supported, ExtFmt- EETLPPrefix- > > + EmergencyPowerReduction Not Supported, > > EmergencyPowerReductionInit- > > + FRS- > > + DevCtl2: Completion Timeout: 50us to 50ms, > > TimeoutDis- LTR- OBFF Disabled, > > + Capabilities: [80] Power Management version 3 > > + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0- > > ,D1-,D2-,D3hot-,D3cold-) > > + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 > > PME- > > + Capabilities: [90] MSI: Enable- Count=1/1 Maskable+ 64bit- > > + Address: 00000000 Data: 0000 > > + Masking: 00000000 Pending: 00000000 > > + Capabilities: [100 v1] Advanced Error Reporting > > + UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- > > UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- > > + UEMsk: DLP- SDES+ TLP- FCP- CmpltTO- CmpltAbrt- > > UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol- > > + UESvrt: DLP+ SDES- TLP+ FCP+ CmpltTO- CmpltAbrt- > > UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- > > + CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- > > AdvNonFatalErr- > > + CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- > > AdvNonFatalErr+ > > + AERCap: First Error Pointer: 00, ECRCGenCap- > > ECRCGenEn- ECRCChkCap- ECRCChkEn- > > + MultHdrRecCap- MultHdrRecEn- TLPPfxPres- > > HdrLogCap- > > + HeaderLog: 00000000 00000000 00000000 00000000 > > + RootCmd: CERptEn- NFERptEn- FERptEn- > > + RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd- > > + FirstFatal- NonFatalMsg- FatalMsg- IntMsg > > 0 > > + ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000 > > + Capabilities: [160 v2] Root Complex Event Collector > > Endpoint Association > > + RCiEPBitmap: RCiEP at Device(s): 0, 1, 4, 7, 8, 9, > > 10, 12, 13 > > + RCECLastBus=00 RCECFirstBus=ff > > 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On Wed, 2020-06-24 at 12:44 -0700, Sean V Kelley wrote: > That works well, I can also add the hyphen if it is adjacent with > this, > I think: > > for (int dev=0; dev < 32; dev++) > { > if (BITS(bmap, dev, 1)) > { > if (!adjcount) > printf("%s %u", (prevmatched) ? "," : "", dev); > prevmatched=1; > adjcount++; > prevdev=dev; > } > else > { > if (adjcount > 1) > printf("-%u", prevdev); > adjacent=0; Rather, I meant: adjcount=0; > } > } > >
diff --git a/lib/header.h b/lib/header.h index 472816e..57a9343 100644 --- a/lib/header.h +++ b/lib/header.h @@ -219,7 +219,7 @@ #define PCI_EXT_CAP_ID_PB 0x04 /* Power Budgeting */ #define PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */ #define PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declaration */ -#define PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */ +#define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */ #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */ #define PCI_EXT_CAP_ID_VC2 0x09 /* Virtual Channel (2nd ID) */ #define PCI_EXT_CAP_ID_RCRB 0x0a /* Root Complex Register Block */ @@ -1048,6 +1048,12 @@ #define PCI_RCLINK_LINK_ADDR 8 /* Link Entry: Address (64-bit) */ #define PCI_RCLINK_LINK_SIZE 16 /* Link Entry: sizeof */ +/* Root Complex Event Collector Endpoint Association */ +#define PCI_RCEC_EP_CAP_VER(reg) (((reg) >> 16) & 0xf) +#define PCI_RCEC_BUSN_REG_VER 0x02 /* as per PCIe sec 7.9.10.1 */ +#define PCI_RCEC_RCIEP_BMAP 0x0004 /* as per PCIe sec 7.9.10.2 */ +#define PCI_RCEC_BUSN_REG 0x0008 /* as per PCIe sec 7.9.10.3 */ + /* PCIe Vendor-Specific Capability */ #define PCI_EVNDR_HEADER 4 /* Vendor-Specific Header */ #define PCI_EVNDR_REGISTERS 8 /* Vendor-Specific Registers */ diff --git a/ls-ecaps.c b/ls-ecaps.c index e71209e..ae26393 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -634,6 +634,52 @@ cap_rclink(struct device *d, int where) } } +static void +cap_rcec(struct device *d, int where) +{ + printf("Root Complex Event Collector Endpoint Association\n"); + if (verbose < 2) + return; + + if (!config_fetch(d, where, 12)) + return; + + u32 hdr = get_conf_long(d, where); + byte cap_ver = PCI_RCEC_EP_CAP_VER(hdr); + u32 bmap = get_conf_long(d, where + PCI_RCEC_RCIEP_BMAP); + printf("\t\tRCiEPBitmap: "); + if (bmap) + { + int dev=0; + int prevmatched=0; + printf("RCiEP at Device(s):"); + while (bmap) + { + if (BITS(bmap, 0, 1)) + if (!prevmatched) + { + prevmatched=1; + printf(" %u", dev); + } + else + printf("%s %u", (prevmatched) ? "," : "", dev); + bmap >>= 1; + dev += 1; + } + } + else + printf("00000000"); + printf("\n"); + + if (cap_ver < PCI_RCEC_BUSN_REG_VER) + return; + + u32 busn = get_conf_long(d, where + PCI_RCEC_BUSN_REG); + printf("\t\tRCECLastBus=%02x RCECFirstBus=%02x\n", + BITS(busn, 16, 8), + BITS(busn, 8, 8)); +} + static void cap_dvsec_cxl(struct device *d, int where) { @@ -991,8 +1037,8 @@ show_ext_caps(struct device *d, int type) case PCI_EXT_CAP_ID_RCILINK: printf("Root Complex Internal Link <?>\n"); break; - case PCI_EXT_CAP_ID_RCECOLL: - printf("Root Complex Event Collector <?>\n"); + case PCI_EXT_CAP_ID_RCEC: + cap_rcec(d, where); break; case PCI_EXT_CAP_ID_MFVC: printf("Multi-Function Virtual Channel <?>\n"); diff --git a/setpci.c b/setpci.c index 90ca726..2cb70fa 100644 --- a/setpci.c +++ b/setpci.c @@ -350,7 +350,7 @@ static const struct reg_name pci_reg_names[] = { { 0x20004, 0, 0, "ECAP_PB" }, { 0x20005, 0, 0, "ECAP_RCLINK" }, { 0x20006, 0, 0, "ECAP_RCILINK" }, - { 0x20007, 0, 0, "ECAP_RCECOLL" }, + { 0x20007, 0, 0, "ECAP_RCEC" }, { 0x20008, 0, 0, "ECAP_MFVC" }, { 0x20009, 0, 0, "ECAP_VC2" }, { 0x2000a, 0, 0, "ECAP_RBCB" }, diff --git a/tests/cap-rcec b/tests/cap-rcec new file mode 100644 index 0000000..4196228 --- /dev/null +++ b/tests/cap-rcec @@ -0,0 +1,299 @@ +6a:00.4 Generic system peripheral [0807]: Intel Corporation Device 0b23 + Subsystem: Intel Corporation Device 0000 + Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- + Interrupt: pin A routed to IRQ 255 + NUMA node: 0 + Capabilities: [40] Express (v2) Root Complex Event Collector, MSI 00 + DevCap: MaxPayload 512 bytes, PhantFunc 0 + ExtTag- RBE- + DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend- + RootCap: CRSVisible- + RootCtl: ErrCorrectable+ ErrNon-Fatal+ ErrFatal+ PMEIntEna- CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + DevCap2: Completion Timeout: Not Supported, TimeoutDis- NROPrPrP- LTR- + 10BitTagComp- 10BitTagReq- OBFF Not Supported, ExtFmt- EETLPPrefix- + EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit- + FRS- + DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LTR- OBFF Disabled, + Capabilities: [80] Power Management version 3 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [90] MSI: Enable- Count=1/1 Maskable+ 64bit- + Address: 00000000 Data: 0000 + Masking: 00000000 Pending: 00000000 + Capabilities: [100 v1] Advanced Error Reporting + UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- + UEMsk: DLP- SDES+ TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol- + UESvrt: DLP+ SDES- TLP+ FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- + CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- + CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ + AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- + MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- + HeaderLog: 00000000 00000000 00000000 00000000 + RootCmd: CERptEn- NFERptEn- FERptEn- + RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd- + FirstFatal- NonFatalMsg- FatalMsg- IntMsg 0 + ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000 + Capabilities: [160 v2] Root Complex Event Collector Endpoint Association + RCiEPBitmap: RCiEP at Device(s): 0, 1, 4, 7, 8, 9, 10, 12, 13 + RCECLastBus=00 RCECFirstBus=ff +00: 86 80 23 0b 00 01 10 00 00 00 07 08 00 00 00 00 +10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 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Root Complex Event Collectors provide support for terminating error and PME messages from RCiEPs. This patch provides basic decoding for the lspci RCEC Endpoint Association Extended Capability. See PCIe 5.0-1, sec 7.9.10 for further details. Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com> --- Changes since v1 [1]: - Corrections to commit log wording/abbreviation. - Added mention of Endpoint Association for clarity. - Removed "Desc:" from output as not necessary. - Removed "cap_ver" from output as redundant. - Broke out RCiEP device numbers as a comma separated list. (Bjorn Helgaas) [1] https://lore.kernel.org/linux-pci/20200622230330.799259-1-sean.v.kelley@linux.intel.com/ Thanks, Sean --- lib/header.h | 8 +- ls-ecaps.c | 50 ++++++++- setpci.c | 2 +- tests/cap-rcec | 299 +++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 355 insertions(+), 4 deletions(-) create mode 100644 tests/cap-rcec -- 2.27.0