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[84.0.113.134]) by smtp.gmail.com with ESMTPSA id w3sm11838938edq.65.2020.07.13.09.55.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jul 2020 09:55:14 -0700 (PDT) From: "Saheed O. Bolarinwa" To: skhan@linuxfoundation.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, linux-kernel@vger.kernel.org Cc: Bolarinwa Olayemi Saheed Subject: [PATCH 8/14 v3] PCI/ACPI: Check the return value of pcie_capability_read_*() Date: Mon, 13 Jul 2020 19:55:28 +0200 Message-Id: <20200713175529.29715-4-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20200713175529.29715-1-refactormyself@gmail.com> References: <20200713175529.29715-1-refactormyself@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bolarinwa Olayemi Saheed On failure pcie_capability_read_dword() sets it's last parameter, val to 0. However, with Patch 14/14, it is possible that val is set to ~0 on failure. This would introduce a bug because (x & x) == (~0 & x). This bug can be avoided if the return value of pcie_capability_read_word is checked to confirm success. Check the return value of pcie_capability_read_word() to ensure success. Suggested-by: Bjorn Helgaas Signed-off-by: Bolarinwa Olayemi Saheed Acked-by: Rafael J. Wysocki --- drivers/pci/pci-acpi.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 7224b1e5f2a8..39eb816bc3b8 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -248,12 +248,13 @@ static bool pcie_root_rcb_set(struct pci_dev *dev) { struct pci_dev *rp = pcie_find_root_port(dev); u16 lnkctl; + int ret; if (!rp) return false; - pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl); - if (lnkctl & PCI_EXP_LNKCTL_RCB) + ret = pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl); + if (!ret && (lnkctl & PCI_EXP_LNKCTL_RCB)) return true; return false; @@ -792,12 +793,13 @@ bool pciehp_is_native(struct pci_dev *bridge) { const struct pci_host_bridge *host; u32 slot_cap; + int ret; if (!IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)) return false; - pcie_capability_read_dword(bridge, PCI_EXP_SLTCAP, &slot_cap); - if (!(slot_cap & PCI_EXP_SLTCAP_HPC)) + ret = pcie_capability_read_dword(bridge, PCI_EXP_SLTCAP, &slot_cap); + if (ret || !(slot_cap & PCI_EXP_SLTCAP_HPC)) return false; if (pcie_ports_native)