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[149.200.78.10]) by smtp.gmail.com with ESMTPSA id j5sm9091734ejk.87.2020.07.31.05.02.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Jul 2020 05:02:17 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org, Mike Marciniszyn , Dennis Dalessandro , Doug Ledford , Jason Gunthorpe Cc: "Saheed O. Bolarinwa" , bjorn@helgaas.com, skhan@linuxfoundation.org, linux-kernel-mentees@lists.linuxfoundation.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org Subject: [PATCH v4 01/12] IB/hfi1: Check if pcie_capability_read_*() reads ~0 Date: Fri, 31 Jul 2020 13:02:29 +0200 Message-Id: <20200731110240.98326-2-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200731110240.98326-1-refactormyself@gmail.com> References: <20200731110240.98326-1-refactormyself@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On failure pcie_capability_read_dword() sets it's last parameter, val to 0. In this case dn and up will be 0, so aspm_hw_l1_supported() will return false. However, with Patch 12/12, it is possible that val is set to ~0 on failure. This would introduce a bug because (x & x) == (~0 & x). So with dn and up being 0x02, a true value is return when the read has actually failed. Since, the value ~0 is invalid here, Reset dn and up to 0 when a value of ~0 is read into them, this ensures false is returned on failure in this case. Suggested-by: Bjorn Helgaas Signed-off-by: Saheed O. Bolarinwa --- drivers/infiniband/hw/hfi1/aspm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/infiniband/hw/hfi1/aspm.c b/drivers/infiniband/hw/hfi1/aspm.c index a3c53be4072c..9605b2145d19 100644 --- a/drivers/infiniband/hw/hfi1/aspm.c +++ b/drivers/infiniband/hw/hfi1/aspm.c @@ -33,13 +33,13 @@ static bool aspm_hw_l1_supported(struct hfi1_devdata *dd) return false; pcie_capability_read_dword(dd->pcidev, PCI_EXP_LNKCAP, &dn); - dn = ASPM_L1_SUPPORTED(dn); + dn = (dn == (u32)~0) ? 0 : ASPM_L1_SUPPORTED(dn); pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &up); - up = ASPM_L1_SUPPORTED(up); + up = (up == (u32)~0) ? 0 : ASPM_L1_SUPPORTED(up); /* ASPM works on A-step but is reported as not supported */ - return (!!dn || is_ax(dd)) && !!up; + return (dn || is_ax(dd)) && up; } /* Set L1 entrance latency for slower entry to L1 */