From patchwork Mon Sep 7 12:08:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Smlhbmp1biBXYW5nICjnjovlu7rlhpsp?= X-Patchwork-Id: 11760847 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EBFF059D for ; Mon, 7 Sep 2020 12:11:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C947E2075A for ; Mon, 7 Sep 2020 12:11:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="D0HjMw01" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729033AbgIGMLd (ORCPT ); Mon, 7 Sep 2020 08:11:33 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:33879 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729236AbgIGMK4 (ORCPT ); Mon, 7 Sep 2020 08:10:56 -0400 X-UUID: 2dabae5c51bd471fbdfdd5bd53216433-20200907 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=fV5jHebeyEfLp5i1jQbRfIe1nBzzc22w8CcM/KCSvdQ=; b=D0HjMw0153gFXmvMGuhqSF+aJVaGIwFe2tGOKHvwvTyDa4/EW4+JPjiNb+dugbLmfaS7zGKp2oy7ZX0LNFD9RoRR3ggYfL9YoMYPD5eCzdxM1QWqjDOwH816a+/pzTmq+HB9WfSpBYX6aZKYaqajkrjQHksYAMYp3CEzvJggBiQ=; X-UUID: 2dabae5c51bd471fbdfdd5bd53216433-20200907 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1796186004; Mon, 07 Sep 2020 20:10:52 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 7 Sep 2020 20:10:48 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 7 Sep 2020 20:10:48 +0800 From: Jianjun Wang To: Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Ryder Lee CC: Philipp Zabel , Matthias Brugger , Mauro Carvalho Chehab , , , , , , , Sj Huang , Jianjun Wang Subject: [v1,1/3] dt-bindings: Add YAML schemas for Gen3 PCIe controller Date: Mon, 7 Sep 2020 20:08:50 +0800 Message-ID: <20200907120852.12090-2-jianjun.wang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200907120852.12090-1-jianjun.wang@mediatek.com> References: <20200907120852.12090-1-jianjun.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add YAML schemas documentation for Gen3 PCIe controller on MediaTek SoCs. Acked-by: Ryder Lee Signed-off-by: Jianjun Wang --- .../bindings/pci/mediatek-pcie-gen3.yaml | 158 ++++++++++++++++++ 1 file changed, 158 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml new file mode 100644 index 000000000000..108d29259c05 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Gen3 PCIe controller on MediaTek SoCs + +maintainers: + - Jianjun Wang + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + oneOf: + - const: mediatek,gen3-pcie + - const: mediatek,mt8192-pcie + + device_type: + const: pci + + "#address-cells": + const: 3 + + "#size-cells": + const: 2 + + reg: + items: + - description: Controller control and status registers. + + reg-names: + items: + - const: pcie-mac + + interrupts: + maxItems: 1 + + bus-range: + description: Range of bus numbers associated with this controller. + + ranges: + minItems: 1 + maxItems: 8 + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + anyOf: + - const: mac-rst + - const: phy-rst + + clocks: + maxItems: 5 + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + + phys: + maxItems: 1 + + phy-names: + const: pcie-phy + + '#interrupt-cells': + const: 1 + + interrupt-map-mask: + description: Standard PCI IRQ mapping properties. + + interrupt-map: + description: Standard PCI IRQ mapping properties. + + legacy-interrupt-controller: + description: Interrupt controller node for handling legacy PCI interrupts. + type: object + properties: + "#address-cells": + const: 0 + "#interrupt-cells": + const: 1 + interrupt-controller: true + + required: + - "#address-cells" + - "#interrupt-cells" + - interrupt-controller + +required: + - compatible + - device_type + - "#address-cells" + - "#size-cells" + - reg + - reg-names + - bus-range + - interrupts + - ranges + - clocks + - '#interrupt-cells' + - interrupt-map + - interrupt-map-mask + - legacy-interrupt-controller + +additionalProperties: false + +examples: + - | + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie: pcie@11230000 { + compatible = "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x00 0x11230000 0x00 0x4000>; + reg-names = "pcie-mac"; + interrupts = ; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0x00 0x12000000 0x00 0x12000000 0x00 0x1000000>; + clocks = <&infracfg 40>, + <&infracfg 43>, + <&infracfg 97>, + <&infracfg 99>, + <&infracfg 111>; + assigned-clocks = <&topckgen 50>; + assigned-clock-parents = <&topckgen 91>; + + phys = <&pciephy>; + phy-names = "pcie-phy"; + resets = <&infracfg_rst 0>; + reset-names = "phy-rst"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + pcie_intc: legacy-interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + };