| Message ID | 20201202184659.3795-1-pali@kernel.org (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | [v2] PCI: aardvark: Update comment about disabling link training | expand |
On Wed, 2 Dec 2020 19:46:59 +0100, Pali Rohár wrote: > It is not HW bug or workaround for some cards but it is requirement by PCI > Express spec. After fundamental reset is needed 100ms delay prior enabling > link training. So update comment in code to reflect this requirement. Applied to pci/aardvark, thanks! [1/1] PCI: aardvark: Update comment about disabling link training https://git.kernel.org/lpieralisi/pci/c/1d1cd163d0 Thanks, Lorenzo
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 0be485a25327..f742da2a20ee 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -259,7 +259,14 @@ static void advk_pcie_issue_perst(struct advk_pcie *pcie) if (!pcie->reset_gpio) return; - /* PERST does not work for some cards when link training is enabled */ + /* + * As required by PCI Express spec (PCI Express Base Specification, REV. + * 4.0 PCI Express, February 19 2014, 6.6.1 Conventional Reset) a delay + * for at least 100ms after de-asserting PERST# signal is needed before + * link training is enabled. So ensure that link training is disabled + * prior de-asserting PERST# signal to fulfill that PCI Express spec + * requirement. + */ reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); reg &= ~LINK_TRAINING_EN; advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
It is not HW bug or workaround for some cards but it is requirement by PCI Express spec. After fundamental reset is needed 100ms delay prior enabling link training. So update comment in code to reflect this requirement. Signed-off-by: Pali Rohár <pali@kernel.org> --- Changes in v2: * Add reference to the PCI Express spec --- drivers/pci/controller/pci-aardvark.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)