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[85.76.98.107]) by smtp.gmail.com with ESMTPSA id r201sm6230659lff.268.2020.12.31.04.56.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Dec 2020 04:56:42 -0800 (PST) From: =?utf-8?b?SmFyaSBIw6Rtw6Rsw6RpbmVu?= To: Shawn Lin , Heiko Stuebner Cc: =?utf-8?b?SmFyaSBIw6Rtw6Rsw6RpbmVu?= , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, Lorenzo Pieralisi , Rob Herring , Bjorn Helgaas Subject: [RFC PATCH 2/3] dt-bindings: PCI: rockchip: document bus-scan-delay-ms workaround property Date: Thu, 31 Dec 2020 14:52:13 +0200 Message-Id: <20201231125214.25733-3-nuumiofi@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201231125214.25733-1-nuumiofi@gmail.com> References: <20201231125214.25733-1-nuumiofi@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org New "rockchip,bus-scan-delay-ms" property can be used to set a delay before PCIe bus scan as a workaround for some problematic devices causing a crash in bus scan. Signed-off-by: Jari Hämäläinen --- Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt index af34c65773fd..394bdf562d58 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt +++ b/Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt @@ -57,6 +57,8 @@ Optional Property: using 24MHz OSC for RC's PHY. - ep-gpios: contain the entry for pre-reset GPIO - num-lanes: number of lanes to use +- rockchip,bus-scan-delay-ms: delay before PCIe bus scan in milliseconds. + Provides a workaround for some devices causing a crash in bus scan. - vpcie12v-supply: The phandle to the 12v regulator to use for PCIe. - vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe. - vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe. @@ -106,6 +108,7 @@ pcie0: pcie@f8000000 { <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>; reset-names = "core", "mgmt", "mgmt-sticky", "pipe", "pm", "pclk", "aclk"; + rockchip,bus-scan-delay-ms = <1100>; /* deprecated legacy PHY model */ phys = <&pcie_phy>; phy-names = "pcie-phy";