| Message ID | 20210113114001.5804-2-jianjun.wang@mediatek.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Lorenzo Pieralisi |
| Headers | show |
| Series | PCI: mediatek: Add new generation controller support | expand |
On Wed, Jan 13, 2021 at 07:39:55PM +0800, Jianjun Wang wrote: > Add YAML schemas documentation for Gen3 PCIe controller on > MediaTek SoCs. > > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> > Acked-by: Ryder Lee <ryder.lee@mediatek.com> > --- > .../bindings/pci/mediatek-pcie-gen3.yaml | 172 ++++++++++++++++++ > 1 file changed, 172 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > new file mode 100644 > index 000000000000..f133fb0184f1 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > @@ -0,0 +1,172 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Gen3 PCIe controller on MediaTek SoCs > + > +maintainers: > + - Jianjun Wang <jianjun.wang@mediatek.com> > + > +description: |+ > + PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed > + and compatible with Gen2, Gen1 speed. > + > + This PCIe controller supports up to 256 MSI vectors, the MSI hardware > + block diagram is as follows: > + > + +-----+ > + | GIC | > + +-----+ > + ^ > + | > + port->irq > + | > + +-+-+-+-+-+-+-+-+ > + |0|1|2|3|4|5|6|7| (PCIe intc) > + +-+-+-+-+-+-+-+-+ > + ^ ^ ^ > + | | ... | > + +-------+ +------+ +-----------+ > + | | | > + +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+ > + |0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets) > + +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+ > + ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ > + | | | | | | | | | | | | (MSI vectors) > + | | | | | | | | | | | | > + > + (MSI SET0) (MSI SET1) ... (MSI SET7) > + > + With 256 MSI vectors supported, the MSI vectors are composed of 8 sets, > + each set has its own address for MSI message, and supports 32 MSI vectors > + to generate interrupt. > + > +allOf: > + - $ref: /schemas/pci/pci-bus.yaml# > + > +properties: > + compatible: > + const: mediatek,mt8192-pcie > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + ranges: > + minItems: 1 > + maxItems: 8 > + > + resets: > + minItems: 1 > + maxItems: 2 Why the range? The SoC either has the reset lines or it doesn't. > + > + reset-names: > + anyOf: > + - const: mac > + - const: phy I don't think this should stay, but if so, better expressed like this: minItems: 1 maxItems: 2 items: enum: [ mac, phy ] > + > + clocks: > + maxItems: 6 > + > + clock-names: > + items: > + - const: pl_250m > + - const: tl_26m > + - const: tl_96m > + - const: tl_32k > + - const: peri_26m > + - const: top_133m > + > + assigned-clocks: > + maxItems: 1 > + > + assigned-clock-parents: > + maxItems: 1 > + > + phys: > + maxItems: 1 > + > + '#interrupt-cells': > + const: 1 > + > + interrupt-controller: > + description: Interrupt controller node for handling legacy PCI interrupts. > + type: object > + properties: > + '#address-cells': > + const: 0 > + '#interrupt-cells': > + const: 1 > + interrupt-controller: true > + > + required: > + - '#address-cells' > + - '#interrupt-cells' > + - interrupt-controller > + > + additionalProperties: false > + > +required: > + - compatible > + - reg > + - interrupts > + - ranges > + - clocks > + - '#interrupt-cells' > + - interrupt-controller > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pcie: pcie@11230000 { > + compatible = "mediatek,mt8192-pcie"; > + device_type = "pci"; > + #address-cells = <3>; > + #size-cells = <2>; > + reg = <0x00 0x11230000 0x00 0x4000>; > + reg-names = "pcie-mac"; Not documented. Drop. > + interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; > + bus-range = <0x00 0xff>; > + ranges = <0x82000000 0x00 0x12000000 0x00 > + 0x12000000 0x00 0x1000000>; > + clocks = <&infracfg 44>, > + <&infracfg 40>, > + <&infracfg 43>, > + <&infracfg 97>, > + <&infracfg 99>, > + <&infracfg 111>; > + clock-names = "pl_250m", "tl_26m", "tl_96m", > + "tl_32k", "peri_26m", "top_133m"; > + assigned-clocks = <&topckgen 50>; > + assigned-clock-parents = <&topckgen 91>; > + > + phys = <&pciephy>; > + phy-names = "pcie-phy"; > + resets = <&infracfg_rst 0>; > + reset-names = "phy"; > + > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0x7>; > + interrupt-map = <0 0 0 1 &pcie_intc 0>, > + <0 0 0 2 &pcie_intc 1>, > + <0 0 0 3 &pcie_intc 2>, > + <0 0 0 4 &pcie_intc 3>; > + pcie_intc: interrupt-controller { > + #address-cells = <0>; > + #interrupt-cells = <1>; > + interrupt-controller; > + }; > + }; > + }; > -- > 2.25.1 >
On Mon, 2021-01-25 at 14:22 -0600, Rob Herring wrote: > On Wed, Jan 13, 2021 at 07:39:55PM +0800, Jianjun Wang wrote: > > Add YAML schemas documentation for Gen3 PCIe controller on > > MediaTek SoCs. > > > > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> > > Acked-by: Ryder Lee <ryder.lee@mediatek.com> > > --- > > .../bindings/pci/mediatek-pcie-gen3.yaml | 172 ++++++++++++++++++ > > 1 file changed, 172 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > > > > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > > new file mode 100644 > > index 000000000000..f133fb0184f1 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > > @@ -0,0 +1,172 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Gen3 PCIe controller on MediaTek SoCs > > + > > +maintainers: > > + - Jianjun Wang <jianjun.wang@mediatek.com> > > + > > +description: |+ > > + PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed > > + and compatible with Gen2, Gen1 speed. > > + > > + This PCIe controller supports up to 256 MSI vectors, the MSI hardware > > + block diagram is as follows: > > + > > + +-----+ > > + | GIC | > > + +-----+ > > + ^ > > + | > > + port->irq > > + | > > + +-+-+-+-+-+-+-+-+ > > + |0|1|2|3|4|5|6|7| (PCIe intc) > > + +-+-+-+-+-+-+-+-+ > > + ^ ^ ^ > > + | | ... | > > + +-------+ +------+ +-----------+ > > + | | | > > + +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+ > > + |0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets) > > + +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+ > > + ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ > > + | | | | | | | | | | | | (MSI vectors) > > + | | | | | | | | | | | | > > + > > + (MSI SET0) (MSI SET1) ... (MSI SET7) > > + > > + With 256 MSI vectors supported, the MSI vectors are composed of 8 sets, > > + each set has its own address for MSI message, and supports 32 MSI vectors > > + to generate interrupt. > > + > > +allOf: > > + - $ref: /schemas/pci/pci-bus.yaml# > > + > > +properties: > > + compatible: > > + const: mediatek,mt8192-pcie > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + ranges: > > + minItems: 1 > > + maxItems: 8 > > + > > + resets: > > + minItems: 1 > > + maxItems: 2 > > Why the range? The SoC either has the reset lines or it doesn't. > > > + > > + reset-names: > > + anyOf: > > + - const: mac > > + - const: phy > > I don't think this should stay, but if so, better expressed like this: > > minItems: 1 > maxItems: 2 > items: > enum: [ mac, phy ] Hi Rob, Thanks for your review, does this means that I should merge the resets and reset-names together as the following property? resets: minItems: 1 maxItems: 2 items: enum: [ mac, phy ] > > > > + > > + clocks: > > + maxItems: 6 > > + > > + clock-names: > > + items: > > + - const: pl_250m > > + - const: tl_26m > > + - const: tl_96m > > + - const: tl_32k > > + - const: peri_26m > > + - const: top_133m > > + > > + assigned-clocks: > > + maxItems: 1 > > + > > + assigned-clock-parents: > > + maxItems: 1 > > + > > + phys: > > + maxItems: 1 > > + > > + '#interrupt-cells': > > + const: 1 > > + > > + interrupt-controller: > > + description: Interrupt controller node for handling legacy PCI interrupts. > > + type: object > > + properties: > > + '#address-cells': > > + const: 0 > > + '#interrupt-cells': > > + const: 1 > > + interrupt-controller: true > > + > > + required: > > + - '#address-cells' > > + - '#interrupt-cells' > > + - interrupt-controller > > + > > + additionalProperties: false > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - ranges > > + - clocks > > + - '#interrupt-cells' > > + - interrupt-controller > > + > > +unevaluatedProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + #include <dt-bindings/interrupt-controller/irq.h> > > + > > + bus { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + pcie: pcie@11230000 { > > + compatible = "mediatek,mt8192-pcie"; > > + device_type = "pci"; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + reg = <0x00 0x11230000 0x00 0x4000>; > > + reg-names = "pcie-mac"; > > Not documented. Drop. I will add the property information for reg-names in the next version, it's used by controller driver to get the register resource. Thanks. > > > + interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; > > + bus-range = <0x00 0xff>; > > + ranges = <0x82000000 0x00 0x12000000 0x00 > > + 0x12000000 0x00 0x1000000>; > > + clocks = <&infracfg 44>, > > + <&infracfg 40>, > > + <&infracfg 43>, > > + <&infracfg 97>, > > + <&infracfg 99>, > > + <&infracfg 111>; > > + clock-names = "pl_250m", "tl_26m", "tl_96m", > > + "tl_32k", "peri_26m", "top_133m"; > > + assigned-clocks = <&topckgen 50>; > > + assigned-clock-parents = <&topckgen 91>; > > + > > + phys = <&pciephy>; > > + phy-names = "pcie-phy"; > > + resets = <&infracfg_rst 0>; > > + reset-names = "phy"; > > + > > + #interrupt-cells = <1>; > > + interrupt-map-mask = <0 0 0 0x7>; > > + interrupt-map = <0 0 0 1 &pcie_intc 0>, > > + <0 0 0 2 &pcie_intc 1>, > > + <0 0 0 3 &pcie_intc 2>, > > + <0 0 0 4 &pcie_intc 3>; > > + pcie_intc: interrupt-controller { > > + #address-cells = <0>; > > + #interrupt-cells = <1>; > > + interrupt-controller; > > + }; > > + }; > > + }; > > -- > > 2.25.1 > > > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml new file mode 100644 index 000000000000..f133fb0184f1 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Gen3 PCIe controller on MediaTek SoCs + +maintainers: + - Jianjun Wang <jianjun.wang@mediatek.com> + +description: |+ + PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed + and compatible with Gen2, Gen1 speed. + + This PCIe controller supports up to 256 MSI vectors, the MSI hardware + block diagram is as follows: + + +-----+ + | GIC | + +-----+ + ^ + | + port->irq + | + +-+-+-+-+-+-+-+-+ + |0|1|2|3|4|5|6|7| (PCIe intc) + +-+-+-+-+-+-+-+-+ + ^ ^ ^ + | | ... | + +-------+ +------+ +-----------+ + | | | + +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+ + |0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets) + +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+ + ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ + | | | | | | | | | | | | (MSI vectors) + | | | | | | | | | | | | + + (MSI SET0) (MSI SET1) ... (MSI SET7) + + With 256 MSI vectors supported, the MSI vectors are composed of 8 sets, + each set has its own address for MSI message, and supports 32 MSI vectors + to generate interrupt. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: mediatek,mt8192-pcie + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + ranges: + minItems: 1 + maxItems: 8 + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + anyOf: + - const: mac + - const: phy + + clocks: + maxItems: 6 + + clock-names: + items: + - const: pl_250m + - const: tl_26m + - const: tl_96m + - const: tl_32k + - const: peri_26m + - const: top_133m + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + + phys: + maxItems: 1 + + '#interrupt-cells': + const: 1 + + interrupt-controller: + description: Interrupt controller node for handling legacy PCI interrupts. + type: object + properties: + '#address-cells': + const: 0 + '#interrupt-cells': + const: 1 + interrupt-controller: true + + required: + - '#address-cells' + - '#interrupt-cells' + - interrupt-controller + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - ranges + - clocks + - '#interrupt-cells' + - interrupt-controller + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie: pcie@11230000 { + compatible = "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x00 0x11230000 0x00 0x4000>; + reg-names = "pcie-mac"; + interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0x00 0x12000000 0x00 + 0x12000000 0x00 0x1000000>; + clocks = <&infracfg 44>, + <&infracfg 40>, + <&infracfg 43>, + <&infracfg 97>, + <&infracfg 99>, + <&infracfg 111>; + clock-names = "pl_250m", "tl_26m", "tl_96m", + "tl_32k", "peri_26m", "top_133m"; + assigned-clocks = <&topckgen 50>; + assigned-clock-parents = <&topckgen 91>; + + phys = <&pciephy>; + phy-names = "pcie-phy"; + resets = <&infracfg_rst 0>; + reset-names = "phy"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + };