From patchwork Mon Mar 8 12:20:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 12122097 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16F99C433E0 for ; Mon, 8 Mar 2021 12:21:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CED39651DD for ; Mon, 8 Mar 2021 12:21:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231215AbhCHMUy (ORCPT ); Mon, 8 Mar 2021 07:20:54 -0500 Received: from mga07.intel.com ([134.134.136.100]:3493 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230242AbhCHMUs (ORCPT ); Mon, 8 Mar 2021 07:20:48 -0500 IronPort-SDR: zkUiqrQjEn+qsCEUJOSCwPBFYADH3AvbGWl90alNjaCWh9m67sIHP/PnhPKtq+fAoKxeEOgGqD 9gfzXoVSxu/Q== X-IronPort-AV: E=McAfee;i="6000,8403,9916"; a="252044308" X-IronPort-AV: E=Sophos;i="5.81,232,1610438400"; d="scan'208";a="252044308" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2021 04:20:46 -0800 IronPort-SDR: 7A2Xp3zdMiKu2m4t0oKO7pSq1WMAbOBCWTQ3WUNeykqhEmg3sYAOZ+wTPFd3uu1VlYSRbeNBri ZfnE2o8+QO4w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,232,1610438400"; d="scan'208";a="602124729" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga005.fm.intel.com with ESMTP; 08 Mar 2021 04:20:43 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 2B596565; Mon, 8 Mar 2021 14:20:38 +0200 (EET) From: Andy Shevchenko To: Wolfram Sang , Jean Delvare , Lee Jones , Andy Shevchenko , Tan Jui Nee , Jim Quinlan , Jonathan Yong , Bjorn Helgaas , linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jean Delvare , Peter Tyser , hdegoede@redhat.com, henning.schild@siemens.com Subject: [PATCH v1 5/7] mfd: lpc_ich: Switch to generic pci_p2sb_bar() Date: Mon, 8 Mar 2021 14:20:18 +0200 Message-Id: <20210308122020.57071-6-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210308122020.57071-1-andriy.shevchenko@linux.intel.com> References: <20210308122020.57071-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Instead of open coding pci_p2sb_bar() functionality we are going to use generic library for that. There one more user of it is coming. Besides cleaning up it fixes a potential issue if, by some reason, SPI bar is 64-bit. Signed-off-by: Andy Shevchenko --- drivers/mfd/Kconfig | 1 + drivers/mfd/lpc_ich.c | 20 ++++++-------------- 2 files changed, 7 insertions(+), 14 deletions(-) diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index a03de3f7a8ed..c16bec1852e5 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -553,6 +553,7 @@ config LPC_ICH tristate "Intel ICH LPC" depends on PCI select MFD_CORE + select PCI_P2SB if X86 help The LPC bridge function of the Intel ICH provides support for many functional units. This driver provides needed support for diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c index 3a19ed57260e..8e9bd6813287 100644 --- a/drivers/mfd/lpc_ich.c +++ b/drivers/mfd/lpc_ich.c @@ -42,6 +42,7 @@ #include #include #include +#include #include #include #include @@ -69,8 +70,6 @@ #define BCR 0xdc #define BCR_WPD BIT(0) -#define SPIBASE_APL_SZ 4096 - #define GPIOBASE_ICH0 0x58 #define GPIOCTRL_ICH0 0x5C #define GPIOBASE_ICH6 0x48 @@ -1126,26 +1125,19 @@ static int lpc_ich_init_spi(struct pci_dev *dev) break; case INTEL_SPI_BXT: { - unsigned int p2sb = PCI_DEVFN(13, 0); unsigned int spi = PCI_DEVFN(13, 2); - struct pci_bus *bus = dev->bus; + int ret; /* * The P2SB is hidden by BIOS and we need to unhide it in * order to read BAR of the SPI flash device. Once that is * done we hide it again. */ - pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x0); - pci_bus_read_config_dword(bus, spi, PCI_BASE_ADDRESS_0, - &spi_base); - if (spi_base != ~0) { - res->start = spi_base & 0xfffffff0; - res->end = res->start + SPIBASE_APL_SZ - 1; - - lpc_ich_test_spi_write(dev, spi, info); - } + ret = pci_p2sb_bar(dev, spi, res); + if (ret) + return ret; - pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x1); + lpc_ich_test_spi_write(dev, spi, info); break; }