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[199.19.111.227]) by smtp.gmail.com with ESMTPSA id r19sm9440274pfh.152.2021.06.18.23.40.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Jun 2021 23:40:20 -0700 (PDT) From: Artem Lapkin X-Google-Original-From: Artem Lapkin To: narmstrong@baylibre.com Cc: yue.wang@Amlogic.com, khilman@baylibre.com, lorenzo.pieralisi@arm.com, robh@kernel.org, kw@linux.com, jbrunet@baylibre.com, christianshewitt@gmail.com, martin.blumenstingl@googlemail.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, art@khadas.com, nick@khadas.com, gouwa@khadas.com Subject: [PATCH 2/4] PCI: core: quirks: add mrrs_limit_quirk Date: Sat, 19 Jun 2021 14:39:50 +0800 Message-Id: <20210619063952.2008746-3-art@khadas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619063952.2008746-1-art@khadas.com> References: <20210619063952.2008746-1-art@khadas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Prepare new MRRS limit quirk which can replace dublicated functionality for some controllers from Loongson, Keystone, DesignWare Signed-off-by: Artem Lapkin --- drivers/pci/quirks.c | 54 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 653660e3b..73344ec71 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -5612,3 +5612,57 @@ static void apex_pci_fixup_class(struct pci_dev *pdev) } DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a, PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class); + +/* + * Some Loongson PCIe ports have a h/w limitation of + * 256 bytes maximum read request size... + * + * Keystone PCI controller has a h/w limitation of + * 256 bytes maximum read request size. + * + * Amlogic DesignWare PCI controller on Khadas VIM3/VIM3L have some + * issue with HDMI scrambled picture and nvme devices + * at intensive writing... + */ +static void mrrs_limit_quirk(struct pci_dev *dev) +{ + struct pci_bus *bus = dev->bus; + struct pci_dev *bridge; + int mrrs; + int mrrs_limit = 256; + static const struct pci_device_id bridge_devids[] = { + { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_PCIE_PORT_0) }, + { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_PCIE_PORT_1) }, + { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_PCIE_PORT_2) }, + { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_RC_K2HK), + .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, + { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_RC_K2E), + .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, + { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_RC_K2L), + .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, + { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_RC_K2G), + .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, + { PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3) }, + { 0, }, + }; + + /* look for the matching bridge */ + while (!pci_is_root_bus(bus)) { + bridge = bus->self; + bus = bus->parent; + /* + * 256 bytes maximum read request size. They can't handle + * anything larger than this. So force this limit on + * any devices attached under these ports. + */ + if (pci_match_id(bridge_devids, bridge)) { + mrrs = pcie_get_readrq(dev); + if (mrrs > mrrs_limit) { + pci_info(dev, "limiting MRRS %d to %d\n", mrrs, mrrs_limit); + pcie_set_readrq(dev, mrrs_limit); + } + break; + } + } +} +DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, mrrs_limit_quirk);