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[199.19.111.227]) by smtp.gmail.com with ESMTPSA id r19sm9440274pfh.152.2021.06.18.23.40.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Jun 2021 23:40:24 -0700 (PDT) From: Artem Lapkin X-Google-Original-From: Artem Lapkin To: narmstrong@baylibre.com Cc: yue.wang@Amlogic.com, khilman@baylibre.com, lorenzo.pieralisi@arm.com, robh@kernel.org, kw@linux.com, jbrunet@baylibre.com, christianshewitt@gmail.com, martin.blumenstingl@googlemail.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, art@khadas.com, nick@khadas.com, gouwa@khadas.com Subject: [PATCH 3/4] PCI: keystone move mrrs quirk to core Date: Sat, 19 Jun 2021 14:39:51 +0800 Message-Id: <20210619063952.2008746-4-art@khadas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619063952.2008746-1-art@khadas.com> References: <20210619063952.2008746-1-art@khadas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Replace dublicated functionality ks_pcie_quirk to mrrs_limit_quirk from core pci quirks Signed-off-by: Artem Lapkin --- drivers/pci/controller/dwc/pci-keystone.c | 49 ----------------------- 1 file changed, 49 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 53aa35cb3..879ae2d4f 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -83,12 +83,6 @@ #define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \ ERR_NONFATAL | ERR_FATAL | ERR_SYS) -/* PCIE controller device IDs */ -#define PCIE_RC_K2HK 0xb008 -#define PCIE_RC_K2E 0xb009 -#define PCIE_RC_K2L 0xb00a -#define PCIE_RC_K2G 0xb00b - #define KS_PCIE_DEV_TYPE_MASK (0x3 << 1) #define KS_PCIE_DEV_TYPE(mode) ((mode) << 1) @@ -521,49 +515,6 @@ static int ks_pcie_start_link(struct dw_pcie *pci) return 0; } -static void ks_pcie_quirk(struct pci_dev *dev) -{ - struct pci_bus *bus = dev->bus; - struct pci_dev *bridge; - static const struct pci_device_id rc_pci_devids[] = { - { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK), - .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, - { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2E), - .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, - { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L), - .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, - { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2G), - .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, - { 0, }, - }; - - if (pci_is_root_bus(bus)) - bridge = dev; - - /* look for the host bridge */ - while (!pci_is_root_bus(bus)) { - bridge = bus->self; - bus = bus->parent; - } - - if (!bridge) - return; - - /* - * Keystone PCI controller has a h/w limitation of - * 256 bytes maximum read request size. It can't handle - * anything higher than this. So force this limit on - * all downstream devices. - */ - if (pci_match_id(rc_pci_devids, bridge)) { - if (pcie_get_readrq(dev) > 256) { - dev_info(&dev->dev, "limiting MRRS to 256\n"); - pcie_set_readrq(dev, 256); - } - } -} -DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk); - static void ks_pcie_msi_irq_handler(struct irq_desc *desc) { unsigned int irq = desc->irq_data.hwirq;