| Message ID | 20210807072409.9018-2-sergio.paracuellos@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
| Series | MIPS: ralink: properly handle pci IO resources | expand |
diff --git a/arch/mips/include/asm/mach-ralink/spaces.h b/arch/mips/include/asm/mach-ralink/spaces.h index 87d085c9ad61..31a3525213cf 100644 --- a/arch/mips/include/asm/mach-ralink/spaces.h +++ b/arch/mips/include/asm/mach-ralink/spaces.h @@ -2,9 +2,7 @@ #ifndef __ASM_MACH_RALINK_SPACES_H_ #define __ASM_MACH_RALINK_SPACES_H_ -#define PCI_IOBASE _AC(0xa0000000, UL) -#define PCI_IOSIZE SZ_16M -#define IO_SPACE_LIMIT (PCI_IOSIZE - 1) +#define IO_SPACE_LIMIT 0x1fffffff #include <asm/mach-generic/spaces.h> #endif
Defining PCI_IOBASE results in pci resource handling working but the addresses generated for IO accesses are wrong since the ioremap in the pci core function 'pci_parse_request_of_pci_ranges' tries to remap to a fixed virtual address (PC_IOBASE) which can't work for KSEG1 addresses. To get it working this way, we would need to put PCI_IOBASE somewhere into KSEG2 which will result in creating TLB entries for IO addresses, which most of the time isn't needed on MIPS because of access via KSEG1. So avoid to define PCI_IOBASE and increase IO_SPACE_LIMIT resource for ralink MIPS platform instead, to get valid IO addresses for resources from pci core 'pci_address_to_pio' function. Fixes: 222b27713d7f ("MIPS: ralink: Define PCI_IOBASE) Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> --- arch/mips/include/asm/mach-ralink/spaces.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-)