| Message ID | 20210819125939.21253-1-jianjun.wang@mediatek.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Lorenzo Pieralisi |
| Headers | show |
| Series | PCI: mediatek-gen3: Disable DVFSRC voltage request | expand |
On Thu, Aug 19, 2021 at 08:59:39PM +0800, Jianjun Wang wrote: > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Reviewed-by: Tzung-Bi Shih <tzungbi@google.com>
Hi Maintainers, Just gentle ping for this patch, if there is anything I need to modify, please kindly let me know. Thanks. On Fri, 2021-08-20 at 11:25 +0800, Tzung-Bi Shih wrote: > On Thu, Aug 19, 2021 at 08:59:39PM +0800, Jianjun Wang wrote: > > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> > > Reviewed-by: Tzung-Bi Shih <tzungbi@google.com>
Hi Bjorn, Lorenzo, Just gentle ping for this patch, please kindly let me know your comments about this patch. Thanks. On Thu, 2021-09-02 at 10:27 +0800, Jianjun Wang wrote: > Hi Maintainers, > > Just gentle ping for this patch, if there is anything I need to > modify, > please kindly let me know. > > Thanks. > > On Fri, 2021-08-20 at 11:25 +0800, Tzung-Bi Shih wrote: > > On Thu, Aug 19, 2021 at 08:59:39PM +0800, Jianjun Wang wrote: > > > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> > > > > Reviewed-by: Tzung-Bi Shih <tzungbi@google.com>
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index f3aeb8d4eaca..79fb12fca6a9 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -79,6 +79,9 @@ #define PCIE_ICMD_PM_REG 0x198 #define PCIE_TURN_OFF_LINK BIT(4) +#define PCIE_MISC_CTRL_REG 0x348 +#define PCIE_DISABLE_DVFSRC_VLT_REQ BIT(1) + #define PCIE_TRANS_TABLE_BASE_REG 0x800 #define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4 #define PCIE_ATR_TRSL_ADDR_LSB_OFFSET 0x8 @@ -297,6 +300,11 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port *port) val &= ~PCIE_INTX_ENABLE; writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG); + /* Disable DVFSRC voltage request */ + val = readl_relaxed(port->base + PCIE_MISC_CTRL_REG); + val |= PCIE_DISABLE_DVFSRC_VLT_REQ; + writel_relaxed(val, port->base + PCIE_MISC_CTRL_REG); + /* Assert all reset signals */ val = readl_relaxed(port->base + PCIE_RST_CTRL_REG); val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB;
When the DVFSRC feature is not implemented, the MAC layer will assert a voltage request signal when exit from the L1ss state, but cannot receive the voltage ready signal, which will cause the link to fail to exit the L1ss state correctly. Disable DVFSRC voltage request by default, we need to find a common way to enable it in the future. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> --- drivers/pci/controller/pcie-mediatek-gen3.c | 8 ++++++++ 1 file changed, 8 insertions(+)