From patchwork Fri Oct 1 19:58:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12531643 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9985C433EF for ; Fri, 1 Oct 2021 19:59:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CFAB061AD1 for ; Fri, 1 Oct 2021 19:59:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240592AbhJAUAt (ORCPT ); Fri, 1 Oct 2021 16:00:49 -0400 Received: from mail.kernel.org ([198.145.29.99]:42946 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229916AbhJAUAs (ORCPT ); Fri, 1 Oct 2021 16:00:48 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 5CE5F61AE1; Fri, 1 Oct 2021 19:59:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1633118343; bh=/0Z/2LEocX5fVRWMKbSKvxT+YnIkYZ2PlxsVs//25oA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Y3RAjOP/A7DXZXsCv1r/Vl9X0ZnWKyWbaF3SrK0rHT57xd20oXIB+6v7YU++Zto2i SltbUT7pDtg/fXpXWXc/naM8L7gz3qkQCp0Bs0esmoViZUhCpc5E9F0CrzKBlw7pnZ SHg8Y7QpzCqHpPT766pT7Z//BiFbBLelBs9hjG5GA0HQ2VbGlAYhw/YajHmzRdDN+h Q3yo/fZWj4DtpcWCCv1s2tvJvsqcvtu5sITVNJwVtuqk/6ncpQNw8ZOZj29hmDm4Mm yGKYZlbH1Qoq/E2nyW28SWsNlHP6nuHyn2ylZwb088KjNCE7OWKnkf5HgAZPV2Umxm 7ZvW7+Omldkng== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi Cc: Thomas Petazzoni , Bjorn Helgaas , linux-pci@vger.kernel.org, pali@kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= , stable@vger.kernel.org Subject: [PATCH 02/13] PCI: aardvark: Fix PCIe Max Payload Size setting Date: Fri, 1 Oct 2021 21:58:45 +0200 Message-Id: <20211001195856.10081-3-kabel@kernel.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211001195856.10081-1-kabel@kernel.org> References: <20211001195856.10081-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár Change PCIe Max Payload Size setting in PCIe Device Control register to 512 bytes to align with PCIe Link Initialization sequence as defined in Marvell Armada 3700 Functional Specification. According to the specification, maximal Max Payload Size supported by this device is 512 bytes. Without this kernel prints suspicious line: pci 0000:01:00.0: Upstream bridge's Max Payload Size set to 256 (was 16384, max 512) With this change it changes to: pci 0000:01:00.0: Upstream bridge's Max Payload Size set to 256 (was 512, max 512) Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver") Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Signed-off-by: Marek Behún Cc: stable@vger.kernel.org --- drivers/pci/controller/pci-aardvark.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 596ebcfcc82d..884510630bae 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -488,8 +488,9 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); reg &= ~PCI_EXP_DEVCTL_RELAX_EN; reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; + reg &= ~PCI_EXP_DEVCTL_PAYLOAD; reg &= ~PCI_EXP_DEVCTL_READRQ; - reg |= PCI_EXP_DEVCTL_PAYLOAD; /* Set max payload size */ + reg |= PCI_EXP_DEVCTL_PAYLOAD_512B; reg |= PCI_EXP_DEVCTL_READRQ_512B; advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);