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Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v1 1/6] PCI/ASPM: Extract out L1SS_CAP calculations Date: Sat, 6 Nov 2021 18:53:48 +0100 Message-Id: <20211106175353.26248-2-refactormyself@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211106175353.26248-1-refactormyself@gmail.com> References: <20211106175353.26248-1-refactormyself@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Inside pcie_aspm_cap_init() the L1SS_CAP of both ends of the link is calculated. The values are used to calculate link->aspm_support and link->aspm_enabled. Isolating this calcution with simplify pcie_aspm_cap_init(). Extract the calculations of L1SS_CAP on both ends into aspm_calc_both_l1ss_caps(). Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/pcie/aspm.c | 42 ++++++++++++++++++++++++----------------- 1 file changed, 25 insertions(+), 17 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 013a47f587ce..057c6768fb7b 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -540,6 +540,30 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, } } +static void aspm_calc_both_l1ss_caps(struct pcie_link_state *link, + u32 *up_l1ss_cap, u32 *dwn_l1ss_cap) +{ + struct pci_dev *child = link->downstream, *parent = link->pdev; + + pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP, + up_l1ss_cap); + pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP, + dwn_l1ss_cap); + + if (!(*up_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) + *up_l1ss_cap = 0; + if (!(*dwn_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) + *dwn_l1ss_cap = 0; + + /* + * If we don't have LTR for the entire path from the Root Complex + * to this device, we can't use ASPM L1.2 because it relies on the + * LTR_L1.2_THRESHOLD. See PCIe r4.0, secs 5.5.4, 6.18. + */ + if (!child->ltr_path) + *dwn_l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2; +} + static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) { struct pci_dev *child = link->downstream, *parent = link->pdev; @@ -606,23 +630,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) link->latency_dw.l1 = calc_l1_latency(child_lnkcap); /* Setup L1 substate */ - pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP, - &parent_l1ss_cap); - pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP, - &child_l1ss_cap); - - if (!(parent_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) - parent_l1ss_cap = 0; - if (!(child_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) - child_l1ss_cap = 0; - - /* - * If we don't have LTR for the entire path from the Root Complex - * to this device, we can't use ASPM L1.2 because it relies on the - * LTR_L1.2_THRESHOLD. See PCIe r4.0, secs 5.5.4, 6.18. - */ - if (!child->ltr_path) - child_l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2; + aspm_calc_both_l1ss_caps(link, &parent_l1ss_cap, &child_l1ss_cap); if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1) link->aspm_support |= ASPM_STATE_L1_1;