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[v2] PCI / thunderbolt: Add quirk to handle incorrect Supported Link Speeds

Message ID 20220110180049.59403-1-sanrio.alvares@intel.com (mailing list archive)
State New, archived
Delegated to: Bjorn Helgaas
Headers show
Series [v2] PCI / thunderbolt: Add quirk to handle incorrect Supported Link Speeds | expand

Commit Message

Sanrio Alvares Jan. 10, 2022, 6 p.m. UTC 
In PCIe config space the "Supported Link Speeds" Vector value is 0x07,
in all downstream ports for Intel Titan Ridge. Which means link
supports Gen1, Gen2 and Gen3. While actually max link speed is 2.5GT/s
so the value of this vector should be 0x01.

As a consequence of reporting >2.5GT/s, we need to delay the full 1s
which makes resuming longer than needed.

Signed-off-by: Sanrio Alvares <sanrio.alvares@intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
---
Changes from v1:
- add static to quirk_intel_tbt_supported_link_speeds
---
 drivers/pci/pci.c    |  4 ++++
 drivers/pci/quirks.c | 14 ++++++++++++++
 include/linux/pci.h  |  1 +
 3 files changed, 19 insertions(+)
diff mbox series

Patch

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 3d2fb394986a..92401552d385 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -6136,6 +6136,10 @@  enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
 {
 	u32 lnkcap2, lnkcap;
 
+	/* Use overridden value of Supported Link Speed */
+	if (dev->supported_link_speed)
+		return dev->supported_link_speed;
+
 	/*
 	 * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18.  The
 	 * implementation note there recommends using the Supported Link
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 003950c738d2..2cbe0beeac08 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -5293,6 +5293,20 @@  static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
 
+/*
+ * Intel Titan Ridge returns incorrect Supported Link Speeds Vector
+ * when max Link Speed is 2.5GT/s. This results in an extra 1s delay during
+ * resume_noirq with pcie tunneling enabled. Override that value:
+ */
+static void quirk_intel_tbt_supported_link_speeds(struct pci_dev *pdev)
+{
+	pci_info(pdev, "applying Supported Link Speeds quirk\n");
+	pdev->supported_link_speed = PCIE_SPEED_2_5GT;
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x15e7, quirk_intel_tbt_supported_link_speeds);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x15ea, quirk_intel_tbt_supported_link_speeds);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x15ef, quirk_intel_tbt_supported_link_speeds);
+
 /*
  * FLR may cause the following to devices to hang:
  *
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 18a75c8e615c..633e81e9fe3b 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -502,6 +502,7 @@  struct pci_dev {
 	struct pci_p2pdma __rcu *p2pdma;
 #endif
 	u16		acs_cap;	/* ACS Capability offset */
+	u8		supported_link_speed; /* Override Supported Link Speed value from device */
 	phys_addr_t	rom;		/* Physical address if not from BAR */
 	size_t		romlen;		/* Length if not from BAR */
 	char		*driver_override; /* Driver name to force a match */