From patchwork Thu Jan 13 10:49:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 12712560 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42D43C433FE for ; Thu, 13 Jan 2022 10:49:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231657AbiAMKtq (ORCPT ); Thu, 13 Jan 2022 05:49:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41860 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233381AbiAMKtq (ORCPT ); Thu, 13 Jan 2022 05:49:46 -0500 Received: from mout-u-107.mailbox.org (mout-u-107.mailbox.org [IPv6:2001:67c:2050:1::465:107]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09765C061748 for ; Thu, 13 Jan 2022 02:49:45 -0800 (PST) Received: from smtp202.mailbox.org (unknown [91.198.250.118]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-107.mailbox.org (Postfix) with ESMTPS id 4JZLm76yT4zQlJ0; Thu, 13 Jan 2022 11:49:43 +0100 (CET) X-Virus-Scanned: amavisd-new at heinlein-support.de From: Stefan Roese To: linux-pci@vger.kernel.org Cc: Bharat Kumar Gogada , Bjorn Helgaas , =?utf-8?q?Pali_Roh=C3=A1r?= , Michal Simek Subject: [PATCH v3 2/2] PCI: xilinx-nwl: Add method to init_platform_service_irqs hook Date: Thu, 13 Jan 2022 11:49:39 +0100 Message-Id: <20220113104939.1635398-3-sr@denx.de> In-Reply-To: <20220113104939.1635398-1-sr@denx.de> References: <20220113104939.1635398-1-sr@denx.de> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bharat Kumar Gogada Add nwl_init_platform_service_irqs() hook to init_platform_service_irqs to register the platform-specific Service Errors IRQs for this PCIe controller to fully support e.g. AER on this platform. Signed-off-by: Bharat Kumar Gogada Signed-off-by: Stefan Roese Cc: Bjorn Helgaas Cc: Pali Rohár Cc: Michal Simek --- drivers/pci/controller/pcie-xilinx-nwl.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 414b679175b3..607d26a395ec 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -24,6 +24,7 @@ #include #include "../pci.h" +#include "../pcie/portdrv.h" /* Bridge core config registers */ #define BRCFG_PCIE_RX0 0x00000000 @@ -806,6 +807,18 @@ static int nwl_pcie_parse_dt(struct nwl_pcie *pcie, return 0; } +static void nwl_init_platform_service_irqs(struct pci_dev *dev, int *irqs, + int plat_mask) +{ + struct pci_host_bridge *bridge; + struct nwl_pcie *pcie; + + bridge = pci_find_host_bridge(dev->bus); + pcie = pci_host_bridge_priv(bridge); + if (plat_mask & PCIE_PORT_SERVICE_AER) + irqs[PCIE_PORT_SERVICE_AER_SHIFT] = pcie->irq_misc; +} + static const struct of_device_id nwl_pcie_of_match[] = { { .compatible = "xlnx,nwl-pcie-2.11", }, {} @@ -857,6 +870,7 @@ static int nwl_pcie_probe(struct platform_device *pdev) bridge->sysdata = pcie; bridge->ops = &nwl_pcie_ops; + bridge->init_platform_service_irqs = nwl_init_platform_service_irqs; if (IS_ENABLED(CONFIG_PCI_MSI)) { err = nwl_pcie_enable_msi(pcie);