From patchwork Tue Jan 25 07:18:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 12723406 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0768C433F5 for ; Tue, 25 Jan 2022 08:47:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379418AbiAYIrf (ORCPT ); Tue, 25 Jan 2022 03:47:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1451850AbiAYIns (ORCPT ); Tue, 25 Jan 2022 03:43:48 -0500 Received: from mout-u-204.mailbox.org (mout-u-204.mailbox.org [IPv6:2001:67c:2050:1::465:204]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A418C06B5AD for ; Mon, 24 Jan 2022 23:18:28 -0800 (PST) Received: from smtp202.mailbox.org (unknown [91.198.250.118]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-204.mailbox.org (Postfix) with ESMTPS id 4JjdVp54DYz9skl; Tue, 25 Jan 2022 08:18:26 +0100 (CET) X-Virus-Scanned: amavisd-new at heinlein-support.de From: Stefan Roese To: linux-pci@vger.kernel.org Cc: Bjorn Helgaas , =?utf-8?q?Pali_Roh=C3=A1r?= , Bharat Kumar Gogada , Michal Simek , Yao Hongbo , Naveen Naidu Subject: [PATCH v4 1/3] PCI/AER: Call pcie_set_ecrc_checking() for each PCIe device Date: Tue, 25 Jan 2022 08:18:18 +0100 Message-Id: <20220125071820.2247260-2-sr@denx.de> In-Reply-To: <20220125071820.2247260-1-sr@denx.de> References: <20220125071820.2247260-1-sr@denx.de> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Make sure that pcie_set_ecrc_checking() is called for each PCIe device, also when it's hot-plugged. This is done by moving pcie_set_ecrc_checking() to pci_aer_init(). Signed-off-by: Stefan Roese Cc: Bjorn Helgaas Cc: Pali Rohár Cc: Bharat Kumar Gogada Cc: Michal Simek Cc: Yao Hongbo Cc: Naveen Naidu Reviewed-by: Pali Rohár --- v4: - New patch drivers/pci/pcie/aer.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 9fa1f97e5b27..5585fefc4d0e 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -387,6 +387,9 @@ void pci_aer_init(struct pci_dev *dev) pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_ERR, sizeof(u32) * n); pci_aer_clear_status(dev); + + /* Enable ECRC checking if enabled and configured */ + pcie_set_ecrc_checking(dev); } void pci_aer_exit(struct pci_dev *dev) @@ -1223,9 +1226,6 @@ static int set_device_error_reporting(struct pci_dev *dev, void *data) pci_disable_pcie_error_reporting(dev); } - if (enable) - pcie_set_ecrc_checking(dev); - return 0; }