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Sat, 5 Feb 2022 08:23:23 -0800 From: Vidya Sagar To: , , , , CC: , , , , , , , , , , , , , , Subject: [PATCH V1 09/10] PCI: Disable MSI for Tegra234 root ports Date: Sat, 5 Feb 2022 21:51:43 +0530 Message-ID: <20220205162144.30240-10-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220205162144.30240-1-vidyas@nvidia.com> References: <20220205162144.30240-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1d871e24-2c2a-438a-b8da-08d9e8c3d8fb X-MS-TrafficTypeDiagnostic: DM4PR12MB5102:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8a6glFM1iRLwoyiPwNBR5z16TWdkGH6kNUcKU39X89yFPimaFRwajmtRmDPsqraQiIDwk/B1tUYPb8bW7+J5j2SIJVHT5wXPkNJLugiuw/dV4CdLhyZTRqVgu+75rSsNSGjNB1ZZaLqlSE5Zvp9A/qe6AuugYYV4FqKq4k+7JIzd9dAQ9Qh4d/dGQ4eqVwcY46AW0eUUz2c9EXbviE4DKR59BX6EnWfQVtjdD0Aejskxt+aFWWVLIH6Wv3cMrYJ6le8Kl/yR3CMOpMWM4B1fKE3LF0I4K2U/DHSxmWOlcrmpkrvitNLOt0ha+8zsPJMV/IZ1HjVIzfndePYIw27iMM1pSmctuKqAtsIj1PxgbpEL20GWOUBdgONj9yKtgV9VqYDRwHMvlkgrH1U5vEYK8S4hAyK4g5LEoo/nRc09qf1RSt8tThNZ2/x7NM9xKzQS/9I8jHEreMCgRBU5TMIDjo5xrRyuofI99rnr3pZHrA/iqjftaoGtiDBppeuHSY5101iCW9dze/rZ9INqomN79Qm6GLukCl8RIPSEIJHY3JyiimLKivaxJ2qzm6Bt7Jg1lk8vCOOqm4ZeFPTRUQBr6NWT6u4OLlbKqiBE9CId/cg2ZwqX0dPBv3UxZUIFeGaPZ1RljR4EMT3JyeVJWERrZ9RlDOIvS3lF4lpbQNT5F1FhuLiDDjKd4Hkgti+ozdOl5a4TbxmswEKFMb7BMrUwoQ== X-Forefront-Antispam-Report: CIP:12.22.5.235;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(40470700004)(36840700001)(46966006)(508600001)(40460700003)(2616005)(81166007)(5660300002)(7416002)(83380400001)(316002)(6666004)(70206006)(82310400004)(336012)(8936002)(8676002)(70586007)(4326008)(47076005)(36756003)(6636002)(54906003)(110136005)(86362001)(7696005)(2906002)(36860700001)(356005)(426003)(1076003)(186003)(26005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Feb 2022 16:23:30.5184 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1d871e24-2c2a-438a-b8da-08d9e8c3d8fb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT027.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5102 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Tegra234 PCIe rootports don't generate MSI interrupts for PME and AER events. Since PCIe spec (Ref: r4.0 sec 7.7.1.2 and 7.7.2.2) doesn't support using a mix of INTx and MSI/MSI-X, MSI needs to be disabled to avoid root ports service drivers registering their respective ISRs with MSI interrupt and to let only INTx be used for all events. Signed-off-by: Vidya Sagar --- drivers/pci/quirks.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index d2dd6a6cda60..3ac5c45e61a1 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2747,6 +2747,15 @@ DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5, DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6, PCI_CLASS_BRIDGE_PCI, 8, pci_quirk_nvidia_tegra_disable_rp_msi); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a, + PCI_CLASS_BRIDGE_PCI, 8, + pci_quirk_nvidia_tegra_disable_rp_msi); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c, + PCI_CLASS_BRIDGE_PCI, 8, + pci_quirk_nvidia_tegra_disable_rp_msi); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e, + PCI_CLASS_BRIDGE_PCI, 8, + pci_quirk_nvidia_tegra_disable_rp_msi); /* * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing