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Sat, 5 Feb 2022 08:22:20 -0800 From: Vidya Sagar To: , , , , CC: , , , , , , , , , , , , , , Subject: [PATCH V1 04/10] dt-bindings: PHY: P2U: Add support for Tegra234 P2U block Date: Sat, 5 Feb 2022 21:51:38 +0530 Message-ID: <20220205162144.30240-5-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220205162144.30240-1-vidyas@nvidia.com> References: <20220205162144.30240-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6493fa70-00a6-44de-0e99-08d9e8c3b2cf X-MS-TrafficTypeDiagnostic: DM5PR12MB1674:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2582; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: vJKN/+pItjH2z7M/eK9i8dsofz98g1CgexWKME5bcvAmnatL65cj33vUXeV2IBw0S9BN7GeTFJ77oQX/pZE5DfUApUQ5hNMrJ57We0IwP+Yr51DzZtpm47wtey5kKjsjjNjC8wBXIajguqxb15rzQtSkIlPt3tBYZg8M+1Sbdoc3jzVstc+IUWpHRBXiygN5/uJntezErIY3h+1oNEtKGpa0v1cAC636YiePpUoXGTp++VvJxRpJg2LUEbYO8yLZyRdTaQH5FVtKt0W/NPgTuG5BzvMZ9NHh258FFe+BglG6ou1e2Tj6cEE22S3IX2FOMxWVGlfRu6AFn7dE24g/ME8DPjMzctBKH5eG0Zw8c4fpDoMqqe1jieWPVdtHEnfOBuWI1jR6+jZ5JxVLmQ+Pqvh4ngxeP9TXW7tSdFZZeL/+YCORfHPx40OvxdmXy669GnF/DMH43+4DpFIFtjYGjygBXkaTPhe7q9BB1ZCfz8AJpAtwWO9UiGKLYQAHwOIDs+vB5dIWJQ81DmafvI09RrxpvGOg2NQ+/ejznIWUsKlEC49vN43vfI/46UWu0ZzMwPYIc4O9D3pWw0kmLdbkF21Fw7IyFSAJEA6lS9gsF9Xc88OR8rE8XycgNu5nC5tMaYSVpGm0/Mzb2oExVTcV0PIMIFYjc07YSlVmPMjzvqrGv04x/oDkdhWpmsP+FjZL1D/p8OWA/j2z5Um3oiWJ12Y//l4yd3pg6Vq2U4zIjQEONQGnTBGg99ZL1fk7gVdtnW/1LwEt+wBmXDW9jm03HWWRa02fQxTHVLkQLpx6jh0YZdDflWAWkmNaK04zxpOC5B1mb42nj5DXH4dygaWFGw== X-Forefront-Antispam-Report: CIP:12.22.5.238;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(40470700004)(36840700001)(46966006)(4326008)(8936002)(70206006)(36860700001)(8676002)(70586007)(36756003)(7696005)(356005)(6666004)(81166007)(508600001)(40460700003)(6636002)(110136005)(47076005)(2906002)(86362001)(83380400001)(5660300002)(7416002)(54906003)(316002)(426003)(2616005)(1076003)(186003)(26005)(82310400004)(336012)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Feb 2022 16:22:26.4723 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6493fa70-00a6-44de-0e99-08d9e8c3b2cf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT005.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1674 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support for Tegra234 P2U (PIPE to UPHY) module block which is a glue module instantiated once for each PCIe lane between Synopsys DesignWare core based PCIe IP and Universal PHY block. Signed-off-by: Vidya Sagar --- .../bindings/phy/phy-tegra194-p2u.yaml | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml index 9a89d05efbda..6ba1f69b1126 100644 --- a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml +++ b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml @@ -4,7 +4,7 @@ $id: "http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: NVIDIA Tegra194 P2U binding +title: NVIDIA Tegra194 & Tegra234 P2U binding maintainers: - Thierry Reding @@ -12,13 +12,17 @@ maintainers: description: > Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High Speed) each interfacing with 12 and 8 P2U instances respectively. + Tegra234 has three PHY bricks namesly HSIO, NVHS and GBE (Gigabit Ethernet) + each interfacing with 8, 8 and 8 P2U instances respectively. A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE - interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe - lane. + interface and PHY of HSIO/NVHS/GBE bricks. Each P2U instance represents one + PCIe lane. properties: compatible: - const: nvidia,tegra194-p2u + oneOf: + - const: nvidia,tegra194-p2u + - const: nvidia,tegra234-p2u reg: maxItems: 1 @@ -28,6 +32,11 @@ properties: items: - const: ctl + nvidia,skip-sz-protect-en: + description: Should be present if two PCIe retimers are present between + the root port and its immediate downstream device. + type: boolean + '#phy-cells': const: 0