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Sat, 5 Feb 2022 08:23:02 -0800 From: Vidya Sagar To: , , , , CC: , , , , , , , , , , , , , , Subject: [PATCH V1 07/10] arm64: tegra: Enable PCIe slots in P3737-0000 board Date: Sat, 5 Feb 2022 21:51:41 +0530 Message-ID: <20220205162144.30240-8-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220205162144.30240-1-vidyas@nvidia.com> References: <20220205162144.30240-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5123f117-5f87-480c-1c22-08d9e8c3cbe4 X-MS-TrafficTypeDiagnostic: PH7PR12MB5654:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1060; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HOsQOLdfEA4P0UgHO6Ts4LAIMV3gn2W0d8AUDYGLeCr5LVDJN0wNkMDcvC5SBiD9QHC2Q1ND3sz/Xs3c6hFSipTgfSmeAylcM8+wDVX5QeD0fFoHwneaV8fzMBbQjQzlUwfZDOXtoRBK6QL9tqgFkdqcTmAVgM7/jy3FUvba9RBAbWJHku363/TYOPaLXcNtyDTJOeL5Tgi1vKpsp58Dqq1ehwbgwl6h7mY6QwPOOfcpV1y09qzhDqON3x4k7xORLXZcAC2ygRwR+qIs7VY0bFnlEIPeSC+WhHZzo00wXWvwoYE1RP+RheLHAIHIl7eHFoBhn5ok+33x6LYAlD30gx9MCGUWkdW6yZ1ie/aEsZy+b4i6Ll1fFo2Umn7vWzsSgKIi5sQ4oTAMOzOWtPInSO1htYAGScG7DB4YfmNrytRC7GmbTxpJSqMSFwR2UZtV0Q7JMPa1WW1uYm+ypF6EYr9BK5upOwpHjDSfb3xegMBxidjL+SSRlMdA8N37IIioAc+ZWkh2dT5LFbo1XDGWMQe3rLZdvrY7paTZDa10p8bKaTtTVQkAqxGyNhiVVIcgm1VgwVvlO4hRnH/kr+JZwGC9ALF86Dzvyvq4XvtHzmolsTJZTlmRd/9gkhLvlTP7BKHkswu3vUN/UqgB0CLk7lMDS2sNsl5HqU4w1X3Iwjm7wbf0G4GE9dr5Sk7oc2XYjNQB+nk6seXLYz9Nv9gscg== X-Forefront-Antispam-Report: CIP:12.22.5.238;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(36840700001)(40470700004)(46966006)(36756003)(70586007)(70206006)(4326008)(8936002)(8676002)(7416002)(110136005)(508600001)(54906003)(40460700003)(86362001)(356005)(81166007)(36860700001)(26005)(426003)(2616005)(336012)(186003)(82310400004)(1076003)(6636002)(316002)(5660300002)(47076005)(6666004)(7696005)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Feb 2022 16:23:08.5533 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5123f117-5f87-480c-1c22-08d9e8c3cbe4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT042.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5654 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Enable PCIe controller nodes to enable respective PCIe slots on P3737-0000 board. Following is the ownership of slots by different PCIe controllers. Controller-1 : On-board Broadcom WiFi controller Controller-4 : M.2 Key-M slot Controller-5 : CEM form-factor x8 slot Signed-off-by: Vidya Sagar --- .../nvidia/tegra234-p3737-0000+p3701-0000.dts | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index efbbb878ba5a..b819e1133bc4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -21,4 +21,30 @@ serial { status = "okay"; }; + + pcie@14100000 { + status = "okay"; + + phys = <&p2u_hsio_3>; + phy-names = "p2u-0"; + }; + + pcie@14160000 { + status = "okay"; + + phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>, + <&p2u_hsio_7>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; + }; + + pcie@141a0000 { + status = "okay"; + + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, + <&p2u_nvhs_6>, <&p2u_nvhs_7>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", + "p2u-5", "p2u-6", "p2u-7"; + }; + };