From patchwork Sun Feb 20 19:33:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12752851 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 514BFC433FE for ; Sun, 20 Feb 2022 19:34:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244660AbiBTTet (ORCPT ); Sun, 20 Feb 2022 14:34:49 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:43556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244654AbiBTTeq (ORCPT ); Sun, 20 Feb 2022 14:34:46 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 770B3522F2 for ; Sun, 20 Feb 2022 11:34:25 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 1265A60EED for ; Sun, 20 Feb 2022 19:34:25 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 670B7C340E8; Sun, 20 Feb 2022 19:34:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1645385664; bh=/PnS26xChDA5R/YR7kt1XShfm9aDXqQ1PCUmLWPS9NQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=p23F61SS/A6CTlR3B8ruMMNQ/J+rEbBDadaEtLw8GomIwF88W90kcvdJoqhGeDORt 1d6IOlKMSqCrZenHzWV3oBkJDTtwXmKfCyveoiBXj9miVTeVvNhHCBDDNTvhSCTixA o6PgEaSclLMoZl2ZLcymvKPKfZCxvzJSd81ch1wX1JGlzspDfcAGEQy0XclaaRSRNI bOdoX665CXsDU4YjqQtvxNbqBJ21w9U9xYQxvVzWiTcZAbGrTK7/2t44+sBV3Zkmwh ugZf2YqzHId3xeDM7FZjhIzvrZcAkmcG1GmnA+hcfrvmTqC2hmV6CqvF6cCW7rCPPe dM6xLFwScRSaw== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Marc Zyngier , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Gregory CLEMENT , Miquel Raynal , =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 14/18] PCI: aardvark: Add clock support Date: Sun, 20 Feb 2022 20:33:42 +0100 Message-Id: <20220220193346.23789-15-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220220193346.23789-1-kabel@kernel.org> References: <20220220193346.23789-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Miquel Raynal The IP relies on a gated clock. When we will add S2RAM support, this clock will need to be resumed before any PCIe registers are accessed. Add support for this clock. Signed-off-by: Miquel Raynal Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- drivers/pci/controller/pci-aardvark.c | 32 +++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 41127a26c5bc..3b51f47abd72 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -8,6 +8,7 @@ * Author: Hezi Shahmoon */ +#include #include #include #include @@ -297,6 +298,7 @@ struct advk_pcie { struct timer_list link_irq_timer; struct pci_bridge_emul bridge; struct gpio_desc *reset_gpio; + struct clk *clk; struct phy *phy; }; @@ -1813,6 +1815,29 @@ static int advk_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return of_irq_parse_and_map_pci(dev, slot, pin); } +static int advk_pcie_setup_clk(struct advk_pcie *pcie) +{ + struct device *dev = &pcie->pdev->dev; + int ret; + + pcie->clk = devm_clk_get(dev, NULL); + if (IS_ERR(pcie->clk) && (PTR_ERR(pcie->clk) == -EPROBE_DEFER)) + return PTR_ERR(pcie->clk); + + /* Old bindings miss the clock handle */ + if (IS_ERR(pcie->clk)) { + dev_warn(dev, "Clock unavailable (%ld)\n", PTR_ERR(pcie->clk)); + pcie->clk = NULL; + return 0; + } + + ret = clk_prepare_enable(pcie->clk); + if (ret) + dev_err(dev, "Clock initialization failed (%d)\n", ret); + + return ret; +} + static void advk_pcie_disable_phy(struct advk_pcie *pcie) { phy_power_off(pcie->phy); @@ -1998,6 +2023,10 @@ static int advk_pcie_probe(struct platform_device *pdev) slot_power_limit / 1000, (slot_power_limit / 100) % 10); + ret = advk_pcie_setup_clk(pcie); + if (ret) + return ret; + ret = advk_pcie_setup_phy(pcie); if (ret) return ret; @@ -2126,6 +2155,9 @@ static int advk_pcie_remove(struct platform_device *pdev) /* Disable phy */ advk_pcie_disable_phy(pcie); + /* Disable clock */ + clk_disable_unprepare(pcie->clk); + return 0; }