[V2,3/8] arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT

Message ID	20220423124858.25946-4-vidyas@nvidia.com (mailing list archive)
State	Superseded
Delegated to:	Lorenzo Pieralisi
Headers	show Return-Path: <linux-pci-owner@kernel.org> Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.236 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.236; helo=mail.nvidia.com; From: Vidya Sagar <vidyas@nvidia.com> To: <bhelgaas@google.com>, <lorenzo.pieralisi@arm.com>, <robh+dt@kernel.org>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com> CC: <kishon@ti.com>, <vkoul@kernel.org>, <kw@linux.com>, <krzk@kernel.org>, <p.zabel@pengutronix.de>, <mperttunen@nvidia.com>, <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-phy@lists.infradead.org>, <kthota@nvidia.com>, <mmaddireddy@nvidia.com>, <vidyas@nvidia.com>, <sagar.tv@gmail.com> Subject: [PATCH V2 3/8] arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT Date: Sat, 23 Apr 2022 18:18:53 +0530 Message-ID: <20220423124858.25946-4-vidyas@nvidia.com> In-Reply-To: <20220423124858.25946-1-vidyas@nvidia.com> References: <20220423124858.25946-1-vidyas@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk
Series	PCI: tegra: Add Tegra234 PCIe support \| expand [V2,0/8] PCI: tegra: Add Tegra234 PCIe support [V2,1/8] dt-bindings: PHY: P2U: Add support for Tegra234 P2U block [V2,2/8] dt-bindings: PCI: tegra: Add device tree support for Tegra234 [V2,3/8] arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT [V2,4/8] arm64: tegra: Enable PCIe slots in P3737-0000 board [V2,5/8] phy: tegra: Add PCIe PIPE2UPHY support for Tegra234 [V2,6/8] PCI: Disable MSI for Tegra234 root ports [V2,7/8] Revert "PCI: tegra194: Rename tegra_pcie_dw to tegra194_pcie" [V2,8/8] PCI: tegra: Add Tegra234 PCIe support

diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 8767dbe2d066..c9200d2c1241 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -907,6 +907,198 @@ status = "okay"; }; + p2u_hsio_0: phy@3e00000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e00000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_1: phy@3e10000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e10000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_2: phy@3e20000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e20000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_3: phy@3e30000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e30000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_4: phy@3e40000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e40000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_5: phy@3e50000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e50000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_6: phy@3e60000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e60000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_7: phy@3e70000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e70000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_0: phy@3e90000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e90000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_1: phy@3ea0000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03ea0000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_2: phy@3eb0000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03eb0000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_3: phy@3ec0000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03ec0000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_4: phy@3ed0000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03ed0000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_5: phy@3ee0000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03ee0000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_6: phy@3ef0000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03ef0000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_7: phy@3f00000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f00000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_gbe_0: phy@3f20000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f20000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_gbe_1: phy@3f30000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f30000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_gbe_2: phy@3f40000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f40000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_gbe_3: phy@3f50000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f50000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_gbe_4: phy@3f60000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f60000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_gbe_5: phy@3f70000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f70000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_gbe_6: phy@3f80000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f80000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_gbe_7: phy@3f90000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f90000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + hsp_aon: hsp@c150000 { compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; reg = <0x0c150000 0x90000>; @@ -1293,6 +1485,589 @@ status = "okay"; }; + pcie@140a0000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; + reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x2a080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; + + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + num-viewport = <8>; + linux,pci-domain = <8>; + + clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; + clock-names = "core"; + + resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, + <&bpmp TEGRA234_RESET_PEX2_CORE_8>; + reset-names = "apb", "core"; + + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + + nvidia,bpmp = <&bpmp 8>; + + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; + + ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ + <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; + + pcie@140c0000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; + reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x2c080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; + + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + num-viewport = <8>; + linux,pci-domain = <9>; + + clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; + clock-names = "core"; + + resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, + <&bpmp TEGRA234_RESET_PEX2_CORE_9>; + reset-names = "apb", "core"; + + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + + nvidia,bpmp = <&bpmp 9>; + + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; + + ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ + <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; + + pcie@140e0000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; + reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x2e080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; + + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + num-viewport = <8>; + linux,pci-domain = <10>; + + clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; + clock-names = "core"; + + resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, + <&bpmp TEGRA234_RESET_PEX2_CORE_10>; + reset-names = "apb", "core"; + + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + + nvidia,bpmp = <&bpmp 10>; + + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; + + ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ + <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; + + pcie@14100000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; + reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; + + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <1>; + num-viewport = <8>; + linux,pci-domain = <1>; + + clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; + clock-names = "core"; + + resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, + <&bpmp TEGRA234_RESET_PEX0_CORE_1>; + reset-names = "apb", "core"; + + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + + nvidia,bpmp = <&bpmp 1>; + + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; + + ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ + <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; + + pcie@14120000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; + reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; + + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <1>; + num-viewport = <8>; + linux,pci-domain = <2>; + + clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; + clock-names = "core"; + + resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, + <&bpmp TEGRA234_RESET_PEX0_CORE_2>; + reset-names = "apb", "core"; + + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + + nvidia,bpmp = <&bpmp 2>; + + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; + + ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ + <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; + + pcie@14140000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; + reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; + + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <1>; + num-viewport = <8>; + linux,pci-domain = <3>; + + clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; + clock-names = "core"; + + resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, + <&bpmp TEGRA234_RESET_PEX0_CORE_3>; + reset-names = "apb", "core"; + + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + + nvidia,bpmp = <&bpmp 3>; + + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; + + ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ + <0x02000000 0x0 0x40000000 0x21 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; + + pcie@14160000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; + reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; + + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + num-viewport = <8>; + linux,pci-domain = <4>; + + clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; + clock-names = "core"; + + resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, + <&bpmp TEGRA234_RESET_PEX0_CORE_4>; + reset-names = "apb", "core"; + + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + + nvidia,bpmp = <&bpmp 4>; + + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; + + ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ + <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; + + pcie@14180000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; + reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; + + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + num-viewport = <8>; + linux,pci-domain = <0>; + + clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; + clock-names = "core"; + + resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, + <&bpmp TEGRA234_RESET_PEX0_CORE_0>; + reset-names = "apb", "core"; + + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + + nvidia,bpmp = <&bpmp 0>; + + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; + + ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ + <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; + + pcie@141a0000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; + reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; + + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <8>; + num-viewport = <8>; + linux,pci-domain = <5>; + + clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; + clock-names = "core"; + + resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, + <&bpmp TEGRA234_RESET_PEX1_CORE_5>; + reset-names = "apb", "core"; + + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + + nvidia,bpmp = <&bpmp 5>; + + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; + + ranges = <0x43000000 0x27 0x40000000 0x27 0x40000000 0x3 0xe8000000>, /* prefetchable memory (16000 MB) */ + <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; + + pcie@141c0000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; + reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x3c080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; + + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + num-viewport = <8>; + linux,pci-domain = <6>; + + clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; + clock-names = "core"; + + resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, + <&bpmp TEGRA234_RESET_PEX1_CORE_6>; + reset-names = "apb", "core"; + + interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; + + nvidia,bpmp = <&bpmp 6>; + + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; + + ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ + <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; + + pcie@141e0000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; + reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x3e080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; + + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <8>; + num-viewport = <8>; + linux,pci-domain = <7>; + + clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; + clock-names = "core"; + + resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, + <&bpmp TEGRA234_RESET_PEX2_CORE_7>; + reset-names = "apb", "core"; + + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + + nvidia,bpmp = <&bpmp 7>; + + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; + + ranges = <0x43000000 0x2e 0x40000000 0x2e 0x40000000 0x3 0xe8000000>, /* prefetchable memory (16000 MB) */ + <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; + sram@40000000 { compatible = "nvidia,tegra234-sysram", "mmio-sram"; reg = <0x0 0x40000000 0x0 0x80000>;

[V2,3/8] arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT

Commit Message

Patch