| Message ID | 20220426132139.26761-2-linux@fw-web.de (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Lorenzo Pieralisi |
| Headers | show |
| Series | RK3568 PCIe V3 support | expand |
On 26/04/2022 15:21, Frank Wunderlich wrote: > From: Frank Wunderlich <frank-w@public-files.de> > > Add a new binding file for Rockchip PCIe v3 phy driver. > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> > > --- > v2: > dt-bindings: rename yaml for PCIe v3 > rockchip-pcie3-phy.yaml => rockchip,pcie3-phy.yaml > > changes in pcie3 phy yaml > - change clock names to ordered const list > - extend pcie30-phymode description > - add phy-cells to required properties > - drop unevaluatedProperties > - example with 1 clock each line > - use default property instead of text describing it > - update license > --- > .../bindings/phy/rockchip,pcie3-phy.yaml | 84 +++++++++++++++++++ > 1 file changed, 84 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > new file mode 100644 > index 000000000000..3592888b5ee2 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > @@ -0,0 +1,84 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip PCIe v3 phy > + > +maintainers: > + - Heiko Stuebner <heiko@sntech.de> > + > +properties: > + compatible: > + enum: > + - rockchip,rk3568-pcie3-phy > + - rockchip,rk3588-pcie3-phy > + > + reg: > + maxItems: 1 > + > + clocks: > + minItems: 1 > + maxItems: 3 > + > + clock-names: > + items: > + - const: "refclk_m" > + - const: "refclk_n" > + - const: "pclk" Drop quotes. > + > + minItems: 1 I think we agreed to skip rk3588 or make the number of clocks strict? > + > + "#phy-cells": > + const: 0 > + > + resets: > + maxItems: 1 > + > + reset-names: > + const: phy > + > + rockchip,phy-grf: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: phandle to the syscon managing the phy "general register files" > + > + rockchip,pipe-grf: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: phandle to the syscon managing the pipe "general register files" > + > + rockchip,pcie30-phymode: > + $ref: '/schemas/types.yaml#/definitions/uint32' No need for quotes. You don't use it in other places. > + description: | > + set the phy-mode for enabling bifurcation > + bit0: bifurcation for port 0 > + bit1: bifurcation for port 1 > + bit2: aggregation > + constants are defined in the dt-bindings/phy/phy-rockchip-pcie3.h Full path. It should also follow vendor,device naming convention. > + minimum: 0x0 > + maximum: 0x4 > + default: 0x4 > + > +required: > + - compatible > + - reg > + - rockchip,phy-grf > + - "#phy-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/rk3568-cru.h> > + pcie30phy: phy@fe8c0000 { > + compatible = "rockchip,rk3568-pcie3-phy"; > + reg = <0x0 0xfe8c0000 0x0 0x20000>; > + #phy-cells = <0>; > + clocks = <&pmucru CLK_PCIE30PHY_REF_M>, > + <&pmucru CLK_PCIE30PHY_REF_N>, > + <&cru PCLK_PCIE30PHY>; > + clock-names = "refclk_m", "refclk_n", "pclk"; > + resets = <&cru SRST_PCIE30PHY>; > + reset-names = "phy"; > + rockchip,phy-grf = <&pcie30_phy_grf>; > + }; Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml new file mode 100644 index 000000000000..3592888b5ee2 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip PCIe v3 phy + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + enum: + - rockchip,rk3568-pcie3-phy + - rockchip,rk3588-pcie3-phy + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 3 + + clock-names: + items: + - const: "refclk_m" + - const: "refclk_n" + - const: "pclk" + + minItems: 1 + + "#phy-cells": + const: 0 + + resets: + maxItems: 1 + + reset-names: + const: phy + + rockchip,phy-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the syscon managing the phy "general register files" + + rockchip,pipe-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the syscon managing the pipe "general register files" + + rockchip,pcie30-phymode: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + set the phy-mode for enabling bifurcation + bit0: bifurcation for port 0 + bit1: bifurcation for port 1 + bit2: aggregation + constants are defined in the dt-bindings/phy/phy-rockchip-pcie3.h + minimum: 0x0 + maximum: 0x4 + default: 0x4 + +required: + - compatible + - reg + - rockchip,phy-grf + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3568-cru.h> + pcie30phy: phy@fe8c0000 { + compatible = "rockchip,rk3568-pcie3-phy"; + reg = <0x0 0xfe8c0000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&pmucru CLK_PCIE30PHY_REF_M>, + <&pmucru CLK_PCIE30PHY_REF_N>, + <&cru PCLK_PCIE30PHY>; + clock-names = "refclk_m", "refclk_n", "pclk"; + resets = <&cru SRST_PCIE30PHY>; + reset-names = "phy"; + rockchip,phy-grf = <&pcie30_phy_grf>; + };