From patchwork Tue May 17 12:50:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12852393 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F4CFC433F5 for ; Tue, 17 May 2022 12:51:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346434AbiEQMvs (ORCPT ); Tue, 17 May 2022 08:51:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51996 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346419AbiEQMvr (ORCPT ); Tue, 17 May 2022 08:51:47 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E7C7541310; Tue, 17 May 2022 05:51:40 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id B71EEBD5; Tue, 17 May 2022 15:52:36 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru B71EEBD5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1652791956; bh=X91Eb7i1pO+lRymwUnCcZj2+zZX4JThyCF/DCQW4gW0=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=IX4B2HB3Ib6XpiNwfQ+1Q62K21PUWcQTzYU2yNSOGc3NCVj4B8iDwm8vIVlMaa0Zc 5TY/jGrB/Lre6WS9SfRSsNOCBu/1VU393CeatwAbk2CKEGJxB63p5t1Fljb5c5ni+A HyzNMR6E7KEhFQwLnTfC6x7oqHDluPlEnjn1ONb8= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 17 May 2022 15:51:39 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= CC: Serge Semin , Serge Semin , Manivannan Sadhasivam , Alexey Malahov , Pavel Parkhomenko , Frank Li , , Subject: [PATCH v3 04/13] PCI: dwc: Disable outbound windows for controllers with iATU Date: Tue, 17 May 2022 15:50:49 +0300 Message-ID: <20220517125058.18488-5-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> References: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org In accordance with the dw_pcie_setup_rc() method semantics and judging by what the comment added in commit dd193929d91e ("PCI: designware: Explain why we don't program ATU for some platforms") states there are DWC PCIe-available platforms like Keystone (pci-keystone.c) or Amazon's Annapurna Labs (pcie-al.c) which don't have the DW PCIe internal ATU enabled and use it's own address translation approach implemented. In these cases at the very least there is no point in touching the DW PCIe iATU CSRs. Moreover depending on the vendor-specific address translation implementation it might be even erroneous. So let's move the iATU windows disabling procedure to being under the corresponding conditional statement clause thus performing that procedure only if the iATU is expected to be available on the platform. Fixes: 458ad06c4cdd ("PCI: dwc: Ensure all outbound ATU windows are reset") Signed-off-by: Serge Semin Reviewed-by: Manivannan Sadhasivam Tested-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-host.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index a250869334a5..4e5c89c19f78 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -572,7 +572,6 @@ static struct pci_ops dw_pcie_ops = { void dw_pcie_setup_rc(struct pcie_port *pp) { - int i; u32 val, ctrl, num_ctrls; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -623,19 +622,22 @@ void dw_pcie_setup_rc(struct pcie_port *pp) PCI_COMMAND_MASTER | PCI_COMMAND_SERR; dw_pcie_writel_dbi(pci, PCI_COMMAND, val); - /* Ensure all outbound windows are disabled so there are multiple matches */ - for (i = 0; i < pci->num_ob_windows; i++) - dw_pcie_disable_atu(pci, i, DW_PCIE_REGION_OUTBOUND); - /* * If the platform provides its own child bus config accesses, it means * the platform uses its own address translation component rather than * ATU, so we should not program the ATU here. */ if (pp->bridge->child_ops == &dw_child_pcie_ops) { - int atu_idx = 0; + int i, atu_idx = 0; struct resource_entry *entry; + /* + * Ensure all outbound windows are disabled so there are + * multiple matches + */ + for (i = 0; i < pci->num_ob_windows; i++) + dw_pcie_disable_atu(pci, i, DW_PCIE_REGION_OUTBOUND); + /* Get last memory resource entry */ resource_list_for_each_entry(entry, &pp->bridge->windows) { if (resource_type(entry->res) != IORESOURCE_MEM)